DDR2 UNBUFFERED SODIMM
VR5DUxx6416xBx
MODULE CONFIGURATIONS
V/I Part Number
VR5DU326416EBP
VR5DU326416EBS
VR5DU326416EBW
VR5DU326416EBY
VR5DU646416EBP
VR5DU646416EBS
VR5DU646416EBW
VR5DU646416EBY
VR5DU646416FBP
VR5DU646416FBS
VR5DU646416FBW
VR5DU646416FBY
VR5DU286416FBP
VR5DU286416FBS
VR5DU286416FBW
VR5DU286416FBY
Capacity
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
Module
Configuration
32Mx64
32Mx64
32Mx64
32Mx64
64Mx64
64Mx64
64Mx64
64Mx64
64Mx64
64Mx64
64Mx64
64Mx64
128Mx64
128Mx64
128Mx64
128Mx64
Device
Configuration
32Mx16 (4)
32Mx16 (4)
32Mx16 (4)
32Mx16 (4)
32Mx16 (8)
32Mx16 (8)
32Mx16 (8)
32Mx16 (8)
64M x 16 (4)
64M x 16 (4)
64M x 16 (4)
64M x 16 (4)
64M x 16 (8)
64M x 16 (8)
64M x 16 (8)
64M x 16 (8)
Module
Ranks
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
Performance
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
CAS
Latency
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL5 (5-5-5)
Features
•
•
•
•
•
•
•
•
•
•
•
•
200 pin SO-DIMM
Single 1.8V
±
0.1V Power Supply
Programmable CAS Latency: 3, 4, 5
Burst Length (4, 8)
Burst type (Sequential & Interleave)
Auto & Self-Refresh.
8k/64ms Refresh Period.
Differential CLK (#CLK) inputs.
On-die termination (ODT)
Off-chip driver (OCD) impedance calibration
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxx6416xBx Revision B Created By: Brian Ouellette
Page 1 of 14
DDR2 UNBUFFERED SODIMM
VR5DUxx6416xBx
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VREF
GND
GND
DQ4
DQ0
DQ5
DQ1
GND
GND
DM0
/DQS0
GND
DQS0
DQ6
GND
DQ7
DQ2
GND
DQ3
DQ12
VSS
DQ13
DQ8
GND
DQ9
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DM1
GND
GND
/DQS1
CK0
DQS1
/CK0
GND
GND
DQ10
DQ14
DQ11
DQ15
GND
GND
GND
GND
DQ16
DQ20
DQ17
DQ21
GND
GND
/DQS2
/EVENT
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
DQS2
DM2
GND
GND
DQ18
DQ22
DQ19
DQ23
GND
GND
DQ24
DQ28
DQ25
DQ29
GND
GND
DM3
/DQS3
NC
DQS3
GND
GND
DQ26
DQ30
DQ27
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ31
GND
GND
CKE0
**CKE1
VDD
VDD
NC
*A15
***BA2
*A14
VDD
VDD
A12
A11
A9
A7
A8
A6
VDD
VDD
A5
A4
A3
A2
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
A1
A0
VDD
VDD
A10/AP
BA1
BA0
/RAS
/WE
/S0
VDD
VDD
/CAS
ODT0
**S1
*A13
VDD
VDD
**ODT1
NC
GND
GND
DQ32
DQ36
DQ33
Pin
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
DQ37
GND
GND
/DQS4
DM4
DQS4
GND
GND
DQ38
DQ34
DQ39
DQ35
GND
GND
DQ44
DQ40
DQ45
DQ41
GND
GND
/DQS5
DM5
DQS5
GND
GND
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
DQ42
DQ46
DQ43
DQ47
GND
GND
DQ48
DQ52
DQ49
DQ53
GND
GND
NC
CK1
GND
/CK1
/DQS6
GND
DQS6
DM6
GND
GND
DQ50
DQ54
DQ51
Pin
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ55
GND
GND
DQ56
DQ60
DQ57
DQ61
GND
GND
DM7
/DQS7
GND
DQS7
DQ58
GND
DQ59
DQ62
GND
DQ63
SDA
GND
SCL
SA0
VDDSPD
SA1
*Pins are not used in this module
** Pins are used in the 2 rank module only
*** Pins are used in the 1Gb based modules only
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxx6416xBx Revision B Created By: Brian Ouellette
Page 2 of 14
DDR2 UNBUFFERED SODIMM
VR5DUxx6416xBx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0, CK1
/CK0, /CK1
CKE0 ~ CKE1
TYPE
IN
POLARITY
Positive Edge
Negative Edge
Active High
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All addresses and control input
signals are sampled on the crossing of the positive edge of CK and negative edge of
/CK. Output data (DQs, DQS and /DQS) is referenced to the crossings of CK and /CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers of the SDRAMs. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or
ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored and previous
operations continue. These input signals also disable all outputs (except CKE and
ODT) of the register(s) on the DIMM when both inputs are high. When both S[0:1] are
high, all register outputs (except CKE, ODT and
Chip select) remain in the previous state.
On-Die Termination control signals
CAS, WE When sampled at the positive rising edge of the clock, /CAS, /RAS, and /WE
define the operation to be executed by the SDRAM.
Reference voltage for SSTL18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank of four or eight is activated.
During a Bank Activate command cycle, Address defines the row address. During a
Read or Write command cycle, Address defines the column address. In addition to the
column address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2
defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
Precharge command cycle, AP is used in conjunction with BA0, BA1, and BA2 to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are
used to define which bank to precharge.
Data Input/Output pins
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
The optional EVENT pin is reserved for use to flag critical module temperatures and is
used in conjunction with a SPD temperature sensing option.
These signals are tied by the host to either VSS or VDDSPD to configure the serial
SPD EEPROM address range.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A
resistor must be connected from the SDA bus line to VDDSPD by the host to act as a
pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD by the host to act as a pull-up.
Serial EEPROM positive power supply (wired to a separate power pin at the connector,
which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and 3.3 Volt)
operations.
IN
/S0 ~ /S1
IN
Active Low
ODT0 ~ ODT1
/RAS, /CAS, /WE
VREF
VDD
BA [2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A [15:0]
IN
-
DQ [63:0]
DM [7:0]
VDD, GND
DQS [7:0]
/DQS [7:0]
/EVENT
SA [1:0]
SDA
SCL
VDDSPD
I/O
IN
Supply
I/O
I/O
Out
IN
I/O
IN
Supply
-
Active High
-
Positive Edge
Negative Edge
-
-
-
-
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxx6416xBx Revision B Created By: Brian Ouellette
Page 3 of 14
DDR2 UNBUFFERED SODIMM
VR5DUxx6416xBx
MECHANICAL OUTLINE
All dimensions are in inches with a tolerance of +/- 0.05 unless otherwise specified.
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxx6416xBx Revision B Created By: Brian Ouellette
Page 4 of 14
DDR2 UNBUFFERED SODIMM
VR5DUxx6416xBx
FUNCTIONAL BLOCK DIAGRAM SINGLE RANK
/CS0
/DQS1
DQS1
DM1
/DQS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDM
LDQS
/LDQS
UDM
UDQS
/UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
/DQS5
DQS5
DM5
/DQS4
DQS4
DM4
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDM
LDQS
/LDQS
UDM
UDQS
/UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D0
D2
/DQS3
DQS3
DM3
/DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDM
LDQS
/LDQS
UDM
UDQS
/UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
BA0~BA2
A0~An
CKE0
/RAS
/CAS
/WE
ODT0
CK0
/CK0
CK1
/CK1
/CS
D1
/DQS7
DQS7
DM7
/DQS6
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDM
LDQS
/LDQS
UDM
UDQS
/UDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D3
BA0~BA2: SDRAMs D0~D3
A0~An: SDRAMs D0~D3
CKE: SDRAMs D0~D3
/RAS: SDRAMs D0~D3
/CAS: SDRAMs D0~D3
/WE: SDRAMs D0~D3
ODT: SDRAMs D0~D3
CK, /CK: SDRAMs D0, D1
CK,/CK:SDRAMs D2, D3
SCL
WP
A0 A1 A2
SA0 SA1 SA2
VDDSPD
VDD/VDDQ
VREF
VSS
SDA
Notes:
The resistor values may vary depending on systems application
Serial PD
D0~D7
D0~D7
D0~D7
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DUxx6416xBx Revision B Created By: Brian Ouellette
Page 5 of 14
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