UTRON
Rev. 1.1
UT62W256C
32K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Rev. 1.0
Rev. 1.1
DESCRIPTION
Original.
1.Add Extended temperature : -20
℃
~85
℃
2.Add order information for lead free product
Draft Date
Aug.13. 2001
Apr. 21. 2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80069
1
UTRON
Rev. 1.1
UT62W256C
32K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62W256C is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology. its
standby current is stable within the range of operating
temperature.
The UT62W256C is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT62W256C operates with wide range power
supply and all inputs and outputs are fully TTL
compatible
FEATURES
Fast access time : 35/70ns
Low power consumption:
Operation : 40/20 mA (max.) (V
CC
≦3.6
V)
50/40 mA (max.) (V
CC
≦5.5
V)
Standby : -L / -LL version
1 / 0.5uA (typical) V
CC
=2.7~3.6V
2 / 1uA (typical) V
CC
=4.5~5.5V
Wide Range power supply: 2.7V~5.5V
Operating temperature :
Commercial temperature : 0
℃
~70
℃
Extended temperature : -20
℃
~85
℃
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8x13.4mm STSOP
PIN CONFIGURATION
A14
1
2
3
28
27
26
Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
32K
×
8
MEMORY
ARRAY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
A13
A8
A9
A11
OE
UT62W256C
4
5
6
7
8
9
10
11
12
13
14
25
24
23
22
21
20
19
18
17
16
15
A0-A14
DECODER
Vcc
Vss
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
I/O2
I/O3
Vss
PDIP/SOP
CE
WE
CONTROL
CIRCUIT
OE
A11
A9
A8
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
A10
OE
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
V
CC
V
SS
WE
Vcc
A14
UT62W256C
21
20
19
18
17
16
15
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
A12
A7
A6
A5
A4
A3
STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80069
2
UTRON
Rev. 1.1
UT62W256C
32K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Commercial
Operation Temperature
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 7.0
0 to 70
-20 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
H = V
IH
, L=V
IL
, X = Don't care.
CE
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
I/O OPERATION
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
℃
to 70
℃
/ -20
℃
to 85
℃
(E))
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
SYMBOL
TEST CONDITION
V
CC
＊
1
V
IH
＊
2
V
IL
I
LI
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC
,
I
LO
V
OH
V
OL
I
CC
MIN. TYP. MAX.
2.7~3.6
2.0
-
V
CC
+0.5
- 0.5
-
0.6
-1
-
1
-1
2.2
-
-
-
-
-
-
-
-
-
-
1
-
0.4
40
20
6
MIN.
TYP. MAX.
4.5~5.5
2.2
-
V
CC
+0.5
- 0.5
-
0.8
-1
-
1
-1
2.4
-
-
-
-
-
-
-
40
30
-
1
-
0.4
50
40
10
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
CE
=V
IH
or
OE
= V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
CE
= V
IL
,I
I/O
=
0mA ,Cycle=Min.
- 35
- 70
Operation Power
Supply Current
I
CC
1
Cycle=1µs
CE
=0.2V;
I
I/O
= 0mA other pins at
0.2V or V
CC
-0.2V
Cycle=500ns
CE
=0.2V
; I
I/O
= 0mA other pins
at 0.2V or V
CC
-0.2V
I
CC
2
I
SB
Standby Power Supply
Current
I
SB1
-
-
-
12
3
40
20
-
-
-
20
3
100
50
mA
mA
µA
µA
CE
=V
IH
CE
≧
V
CC
-0.2V
-L
-LL
-
-
1
0.5
-
-
2
1
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80069
3
UTRON
Rev. 1.1
UT62W256C
32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100Pf+1TTL, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~5.5V , T
A
= 0
℃
to 70
℃
/ -20
℃
to 85
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62W256C-35
MIN.
MAX.
SYMBOL
UT62W256C-35
MIN.
MAX.
UT62W256C-70
MIN.
MAX.
UNIT
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
35
-
-
-
10
5
-
-
5
-
35
35
25
-
-
25
25
-
70
-
-
-
10
5
-
-
5
-
70
70
35
-
-
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
UT62W256C-70
MIN.
MAX.
UNIT
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
35
30
30
0
25
0
20
0
5
-
-
-
-
-
-
-
-
-
-
15
70
60
60
0
50
0
30
0
5
-
-
-
-
-
-
-
-
-
-
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80069
4
UTRON
Rev. 1.1
UT62W256C
32K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
Address
t
AA
t
OH
Dout
Previous data valid
Data Valid
t
OH
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,4,5)
t
RC
Address
t
AA
CE
t
ACE
OE
t
OE
t
CLZ
t
OLZ
Dout
High-Z
Data Valid
t
CHZ
t
OHZ
t
OH
High-Z
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
.
3.Address must be valid prior to or coincident with CE =low
,
; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80069
5
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