UTRON
Rev. 1.1
512K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L5128 is a 4,194,304-bit high speed
CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62L5128 is designed for high speed system
applications.
It is particularly well suited for
battery back-up nonvolatile memory applications.
The UT62L5128 operates from a single
2.7V~3.6V power supply and all inputs and
outputs are fully TTL compatible.
UT62L5128
FEATURES
Access time:55ns(max) for Vcc=3.0V~3.6V
70/100ns(max) for Vcc=2.7V~3.6V
CMOS Low operating power
Operating : 45/35/25mA (Icc max)
Standby : 20µA (TYP.) L-version
3µA (TYP.) LL-version
Single 2.7V~3.6V power supply
Operating Temperature:
Commercial : 0
℃
~70
℃
Extended : -20
℃
~80
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min)
Package : 32-pin 8mm×20mm TSOP-I
32-pin 8mm×13.4mm STSOP
36-pin 6mm×8mm TFBGA
PIN CONFIGURATION
A11
A9
A8
A13
WE
A17
A15
Vcc
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A8
A13
A14
A15
A16
A17
I/O1
I/O8
UT62L5128
.
ROW
DECODER
MEMORY ARRAY
2048 ROWS × 256 COLUMNS × 8bits
VCC
VSS
.
.
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
OE
TSOP-1 / STSOP
.
.
.
.
I/O
CONTROL
.
.
A
B
.
.
.
.
.
.
COLUMN I/O
COLUMN DECODER
A0
I/O5
I/O6
Vss
Vcc
I/O7
I/O8
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O1
I/O2
Vcc
Vss
C
D
CE
WE
LOGIC
CONTROL
OE
A9 A10 A11 A12 A18 A5 A6 A7
E
F
PIN DESCRIPTION
SYMBOL
A0 - A18
I/O1 - I/O8
CE
WE
OE
Vcc
Vss
NC
A18
OE
CE
A17
A16
A12
A15
A13
I/O3
I/O4
A14
G
H
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A10 A11
1
2
3
4
5
6
TFBGA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
1
UTRON
Rev. 1.1
512K X 8 BIT LOW POWER CMOS SRAM
UT62L5128
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High – Z
High – Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
H = V
IH
, L=V
IL
, X = Don't care.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Commercial
Operating Temperature
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
0 to 70
-20 to 80
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, TA =0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
PARAMETER
MIN.
SYMBOL
TEST CONDITION
Power Voltage
Vcc
2.7
Input High Voltage
V
IH
2.0
Input Low Voltage
V
IL
- 0.2
Input Leakage Current
I
LI
-1
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current
I
LO
-1
V
SS
≦
V
I/O
≦
V
CC,
Output Disabled
Output High Voltage
V
OH
I
OH
= - 1mA
2.2
Output Low Voltage
V
OL
I
OL
= 2mA
-
Operating Power
I
CC
Cycle time=Min.100% duty,
55
-
Supply Current
70
-
CE = V
IL
, I
I/O
=0mA ,
100
-
Icc1 Cycle time = 1µs,100% duty,
-
CE
≦
0.2,I
I/O=
0mA,
other pins at 0.2V or Vcc-0.2V,
Icc2 Cycle time =500ns,100% duty,
-
CE
≦
0.2,I
I/O=
0mA
other pins at 0.2V or Vcc-0.2V,
Standby Current(TTL)
I
SB1
-
CE =V
IH
Standby Current(CMOS)
I
SB1
-L
-
CE
≧
V
CC
-0.2V
-
other pins at 0.2V or Vcc-0.2V, -LL
TYP.
3.0
-
-
-
-
-
-
30
25
20
4
MAX.
3.6
Vcc+0.3
0.6
1
1
-
0.4
45
35
25
5
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
8
10
mA
0.3
20
3
0.5
80
25
mA
µA
µA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
2
UTRON
Rev. 1.1
512K X 8 BIT LOW POWER CMOS SRAM
UT62L5128
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , TA =0
℃
to 70
℃
/ -20
℃
to 80
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYMBOL
UT62L5128-55*
UT62L5128-70
UT62L5128-100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
MIN.
55
-
-
-
10
5
-
-
5
MAX.
-
55
55
30
-
-
20
20
-
MIN.
70
-
-
-
10
5
-
-
5
MAX.
-
70
70
35
-
-
25
25
-
MIN.
100
-
-
-
10
5
-
-
5
MAX.
-
100
100
50
-
-
30
35
-
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62L5128-55*
UT62L5128-70
UT62L5128-100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
MIN.
55
50
50
0
45
0
25
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
30
MIN.
70
60
60
0
55
0
30
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
30
MIN.
100
80
80
0
70
0
40
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
40
*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
3
UTRON
Rev. 1.1
512K X 8 BIT LOW POWER CMOS SRAM
UT62L5128
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,5,6)
t
RC
Address
t
AA
CE
t
ACE
OE
t
OE
t
CLZ
D
OUT
High-z
t
OLZ
t
CHZ
t
OHZ
t
OH
Data valid
High-Z
Notes :
WE
is HIGH for read cycle.
2. Device is continuously selected CE =V
IL.
1.
3. Address must be valid prior to or coincident with CE transition; otherwise t
AA
is the limiting parameter.
4. OE is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured
±500mV
from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
Rev. 1.1
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
t
WC
Address
t
AW
CE
512K X 8 BIT LOW POWER CMOS SRAM
UT62L5128
t
AS
WE
t
CW
t
WP
t
WR
t
WHZ
D
OUT
High-Z
t
OW
(4)
(4)
t
DW
t
DH
Data Valid
D
IN
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5)
t
WC
Address
t
AW
CE
t
AS
t
CW
t
WP
t
WR
WE
t
WHZ
D
OUT
High-Z
(4)
t
DW
t
DH
D
IN
Data Valid
Notes :
1.
WE
or CE must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE and a low
WE
.
3. During a
WE
controlled with write cycle with OE LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and
data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high
impedance state.
6. t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
±500mV
from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
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