UTRON
Rev. 1.2
UT62L256C
32K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
DESCRIPTION
Preliminary Rev. 0.1 Original
Rev. 1.0
Sample ready and release
Rev. 1.1
1.Add 28-pin 8x20 mm TSOP-I
2.Add 28L 8x20mm TSOP-I outline dimension
Rev. 1.2
Add order information for lead free product
Date
May 4,2001
Jul 16,2001
Jul 16,2002
May 13,2003
___________________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80057
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
1
UTRON
Rev. 1.2
UT62L256C
32K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L256C is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The UT62L256C is designed for high-speed and
low power application. It is particularly well suited
for battery back-up nonvolatile memory application.
The UT62L256C operates from a single
2.7V ~ 3.6V power supply and all inputs and
outputs are fully TTL compatible
FEATURES
Fast access time : 35/70ns (max.)
Low power consumption:
Operating current : 40/20 mA (max)
Standby current : 1
µA
(typical) L-version
0.5µA(typical) LL-version
Single 2.7V ~ 3.6V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8x13.4mm STSOP
28-pin 8x20 mm TSOP-I
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K
×
8
MEMORY
ARRAY
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
WE
CONTROL
CIRCUIT
OE
___________________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80057
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
2
UTRON
Rev. 1.2
UT62L256C
32K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
28
27
26
Vcc
WE
OE
A11
A9
A8
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A13
A8
A9
A11
OE
UT62L256C
4
5
6
7
8
9
10
11
12
13
14
25
24
23
22
21
20
19
18
17
16
15
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
A10
CE
UT62L256C
21
20
19
18
17
16
15
I/O8
I/O7
I/O6
I/O5
I/O4
PDIP/SOP
STSOP/TSOP-I
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
V
CC
V
SS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
___________________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80057
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
3
UTRON
Rev. 1.2
UT62L256C
32K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.5
0 to 70
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
H = V
IH
, L=V
IL
, X = Don't care.
CE
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
I/O OPERATION
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
CC,
I
cc1,
I
cc2
I
CC,
I
cc1,
I
cc2
I
CC,
I
cc1,
I
cc2
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V ~ 3.6V, T
A
= 0
℃
to 70
℃
)
PARAMETER
SYMBOL TEST CONDITION
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
SS
≦
V
IN
≦
V
CC
Output Leakage
I
LO
V
SS
≦
V
I/O
≦
V
CC
Current
CE =V
IH
or OE = V
IH
or
WE
= V
IL
Output High Voltage
V
OH
I
OH
= - 1mA
Output Low Voltage
V
OL
I
OL
= 4mA
Average Operating
I
CC
Cycle time=Min.,
- 35
Power supply Current
- 70
CE = V
IL
,I
I/O
= 0mA ,
Icc1
Cycle time=1us
CE =0.2V; I
I/O
= 0mA
other pins at 0.2V or Vcc-0.2V;
Icc2
Cycle time=500ns
CE =0.2V; I
I/O
= 0mA
other pins at 0.2V or Vcc-0.2V
Standby Power
I
SB
CE =V
IH
Supply Current
-L
I
SB1
CE
≧
V
CC
-0.2V
-LL
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
___________________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80057
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
MIN.
2.0
- 0.5
-1
-1
TYP.
-
-
-
-
MAX.
V
CC
+0.5
0.6
1
1
UNIT
V
V
µA
µA
2.4
-
-
-
-
-
-
-
-
-
0.4
40
20
-
6
V
V
mA
mA
mA
-
-
12
mA
-
-
-
-
1
0.5
3
40
20
mA
µA
µA
4
UTRON
Rev. 1.2
UT62L256C
32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , T
A
= 0
℃
to 70
℃
)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62L256C-35
MIN.
MAX.
35
-
-
35
-
35
-
25
10
-
5
-
-
25
-
25
5
-
UT62L256C-70
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
35
-
35
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
SYMBOL
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
UT62L256C-35
MIN.
MAX.
35
-
30
-
30
-
0
-
25
-
0
-
20
-
0
-
5
-
-
15
UT62L256C-70
MIN.
MAX.
70
-
60
-
60
-
0
-
50
-
0
-
30
-
0
-
5
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
___________________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80057
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
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