UTRON
Rev. 1.4
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
REVISION HISTORY
REVISION
Rev.1.0
Original
Revised
1. AC TIMING REQUIREMENTS
Input Pulse Levels:0.8V~2.0V 0.4V~2.4V
tIS(min):1, 1.5, 1.3, 2 2, 2.5, 2.5, 2.5ns
tIH(min):1, 0.8, 0.8, 0.8 1, 1, 1, 1ns
2. Output Load Condition
Add Package Outline Dimension
1. Page 1 : add access parameter into “Features”
ITEM
-6 -7
-6
-7 Unit
Rev.1.3
t
CLK
(Min.) CL=2 -
-
10 10 ns
6
6
ns
t
AC
(Max.) CL=2 -
-
t
OH
(Min.) CL=2 -
-
3
3
ns
2. Page 34,35 : add –6ns,-7ns Limits parameters
1. add Operating temperature :
Commercial : 0
℃
~70
℃
Extended : -20
℃
~80
℃
Feb. 10, 2003
DESCRIPTION
DATE
June 20, 2002
Rev.1.1
Jul. 09, 2002
Rev.1.2
Jul. 26, 2002
Rev.1.4
Apr. 25, 2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90006
1
UTRON
Rev. 1.4
DESCRIPTION
UT52L0464 is organized as 4-bank x 4,194,304-
word x 4-bit Synchronous DRAM with LVTTL
interface and UT52L0864 is organized as 4-bank x
2,097,152-word x 8-bit and UT52L1664 is
organized as 4-bank x 1,048,576-word x 16-bit. All
FEATURES
ITEM
tCLK Clock Cycle Time
(Min.)
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
inputs and outputs are referenced to the rising
edge of CLK. UT52L0464, UT52L0864 and
UT52L1664 achieve very high speed data rates up
to 166MHz, and are suitable for main memories or
graphic memories in computer systems.
CL=2
CL=3
tRAS Active to Precharge Command Preiod (Min.)
tRCD Row to Column Delay (Min.)
tAC Access Time from CLK
(Max.)
CL=2
CL=3
UT52L0464
UT52L0864
UT52L1664
-6,-7,-7.5,8
tRC Ref/Active Command Period (Min.)
Icc1 Operation Current(Single Bank) (Max.)
Icc6 Self Refresh Current(Max.)
UT52L0464/0864/1664
-6
-7
-7.5
-8
10ns
10ns
10ns
10ns
6ns
7ns
7.5ns
8ns
42ns
45ns
45ns
48ns
18ns
20ns
20ns
20ns
6ns
6ns
6ns
6ns
5ns
5.4ns
5.4ns
6ns
60ns
63ns
67.5ns
70ns
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
1mA
1mA
1mA
1mA
- Single 3.3V ±0.3V power supply
- Operating temperature :
Commercial : 0
℃
~70
℃
Extended : -20℃~80℃
- Max. Clock frequency -6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-7.5:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (UT52L1664)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90006
2
UTRON
Rev. 1.4
PIN CONFIGURATION(TOP VIEW)
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
UT52L0464
UT52L0864
UT52L1664
PIN CONFIGURATION
(TOP VIEW)
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
400mil 54pin TSOP(II)
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90006
3
UTRON
Rev. 1.4
CLK：Master Clock
CKE：Clock Enable
/CS：Chip Select
/RAS：Row Address Strobe
/CAS：Column Address Strobe
/WE：Write Enable
DQ0-15：Data I/O
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
DQM：Output Disable / Write Mask
A0-11：Address Input
BA0,1：Bank Address
Vdd：Power Supply
VddQ：Power Supply for Output
Vss：Ground
VssQ：Ground for Output
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90006
4
UTRON
Rev. 1.4
BLOCK DIAGRAM
DQ0-7
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
I/O Buffer
Memory Array
4096 X 512 X 8
Cell Array
Bank #0
Memory Array
4096 X 512 X 8
Cell Array
Bank #1
Memory Array
4096 X 512 X 8
Cell Array
Bank #2
Memory Array
4096 X 512 X 8
Cell Array
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS /WE
DQM
Note：This figure shows the UT52L0864
The UT52L0464 configuration is 4096x1024x4 of cell array and DQ0-3
The UT52L1664 configuration is 4096x256x16 of cell array and DQ0-15
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90006
5
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