NT5SV64M4BS / NT5SV64M4BT
NT5SV32M8BS / NT5SV32M8BT
NT5SV16M16BS / NT5SV16M16BT
256Mb Synchronous DRAM
Features
•
High Performance:
6K/6KI
CL=3
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access
Time
1
2
75B/75BI
CL=3
133
7.5
—
5.4
Units
MHz
ns
ns
ns
166
6
—
5
t
AC
Clock Access Time
1. Terminated load. See AC Characteristics on page 37
2. Unterminated load. See AC Characteristics on page 37
3. t
RP
= t
RCD
= 2 CKs
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0/BA1 (Bank Select)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8 or full page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
8192 refresh cycles/64ms
Random Column Address every CK (1-N Rule)
Single 3.3V
±
0.3V Power Supply
LVTTL compatible
Package: 54-pin 400 mil TSOP-Type II
Lead-free & Halogen-free product available
Description
The NT5SV64M4BS, NT5SV64M4BT, NT5SV32M8BS,
NT5SV32M8BT, NT5SV16M16BS, and NT5SV16M16BT are
four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O
x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 166MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Thirteen row addresses (A0-A12) and two
bank select addresses (BA0, BA1) are strobed with RAS.
Eleven column addresses (A0-A9, A11) plus bank select
addresses and A10 are strobed with CAS. Column address
A11 is dropped on the x8 device, and column addresses A11
and A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A12, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
REV 1.7
Oct 2008
1
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV64M4BS / NT5SV64M4BT
NT5SV32M8BS / NT5SV32M8BT
NT5SV16M16BS / NT5SV16M16BT
256Mb Synchronous DRAM
Ordering Information
Speed Grade
Organization
64M x 4
32M x 8
16M x 16
64M x 4
32M x 8
16M x 16
64M x 4
32M x 8
16M x 16
64M x 4
32M x 8
16M x 16
16M x 16
Part Number
NT5SV64M4BS-6K
NT5SV32M8BS-6K
NT5SV16M16BS-6K
NT5SV64M4BS-75B
NT5SV32M8BS-75B
NT5SV16M16BS-75B
NT5SV64M4BT-6K
NT5SV32M8BT-6K
NT5SV16M16BT-6K
NT5SV64M4BT-75B
NT5SV32M8BT-75B
NT5SV16M16BT-75B
NT5SV16M16BS-6KI
NT5SV16M16BS-75BI
NT5SV16M16BT-6KI
NT5SV16M16BT-75BI
166MHz-3-3-3
133MHz-3-3-3
166MHz-3-3-3
133MHz-3-3-3
PC166
PC133
PC166
PC133
400mil
54-PIN TSOP II
Lead-Free
400mil
54-PIN TSOP II
133MHz-3-3-3
PC133
166MHz-3-3-3
PC166
400mil
54-PIN TSOP II
133MHz-3-3-3
PC133
3.3V
166MHz-3-3-3
PC166
400mil
54-PIN TSOP II
Lead-Free
Clock Frequency
CL-t
RCD
-t
RP
Note
Package
Power
3.3V
16M x 16
CL = CAS Latency
Lead-free products are also halogen-free
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
REV 1.7
Oct 2008
2
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV64M4BS / NT5SV64M4BT
NT5SV32M8BS / NT5SV32M8BT
NT5SV16M16BS / NT5SV16M16BT
256Mb Synchronous DRAM
Pin Assignments for Planar Components
(Top View)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
54-pin Plastic TSOP(II) 400 mil
16Mbit x 4 I/O x 4 Bank
8Mbit x 8 I/O x 4 Bank
4Mbit x 16 I/O x 4 Bank
REV 1.7
Oct 2008
3
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV64M4BS / NT5SV64M4BT
NT5SV32M8BS / NT5SV32M8BT
NT5SV16M16BS / NT5SV16M16BT
256Mb Synchronous DRAM
Pin Description
CK
CKE (CKE0, CKE1)
CS
RAS
CAS
WE
BA1, BA0
A0 - A12
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
Input/Output Functional Description
Symbol
CK
CKE, CKE0,
CKE1
CS
RAS, CAS, WE
BA1, BA0
Type
Input
Input
Input
Input
Input
Polarity
Positive
Edge
Active High
Active Low
Active Low
—
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11), when sampled at the rising clock edge. Assume the x4 organization.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10
is low, then BA0 and BA1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
A0 - A12
Input
—
DQ0 - DQ15
Input-
Output
—
DQM
LDQM
UDQM
V
DD
, V
SS
V
DDQ
V
SSQ
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has
a latency of zero and operates as a word mask by allowing input data to be written if it is low but
blocks the write operation if DQM is high.
—
—
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Supply
Supply
REV 1.7
Oct 2008
4
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV64M4BS / NT5SV64M4BT
NT5SV32M8BS / NT5SV32M8BT
NT5SV16M16BS / NT5SV16M16BT
256Mb Synchronous DRAM
Block Diagram
CKE
CKE Buffer
Row Decoder
Column Decoder
Column Decoder
Cell Array
Memory Bank 0
Row Decoder
Cell Array
Memory Bank 1
CK
CK Buffer
Sense Amplifiers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
BA1
BA0
A10
Sense Amplifiers
Data Input/Output Buffers
DQM
Column Decoder
Cell Array
Memory Bank 3
Sense Amplifiers
Address Buffers (15)
Control Signal
Generator
Data Control Circuitry
DQ
0
DQ
X
Refresh
Counter
Column
Address
Counter
Mode Register
Column Decoder
Row Decoder
CS
RAS
CAS
WE
Command Decoder
Cell Array
Memory Bank 2
Sense Amplifiers
Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3).
Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7)
.
Cell Array, per bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15).
REV 1.7
Oct 2008
5
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Row Decoder
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