NT5TU256M4CE / NT5TU128M8CE / NT5TU64M16CG
1Gb DDR2 SDRAM
Features
CAS Latency and Frequency
Speed Sorts
Bin
(CL-tRCD-TRP)
max. Clock
Frequency
Data Rate
CAS Latency
t
RCD
t
RP
t
RC
-37B
DDR2
-533
-3C
DDR2
-667
-AD
DDR2
-800
-AC
DDR2
-800
Units
tck
MHz
Mb/s/pin
tck
ns
ns
ns
• 1KB page size for x 4 & x 8,
2KB page size for x16
• Data-Strobes: Bidirectional, Differential
• Strong and Weak Strength Data-Output Driver
• Auto-Refresh and Self-Refresh
• Power Saving Power-Down modes
• 7.8 µs max. Average Periodic Refresh Interval
4-4-4
266
533
4
15
15
60
5-5-5
333
667
5
15
15
60
6-6-6
400
800
6
15
15
60
5-5-5
400
800
5
12.5
12.5
57.5
• 1.8V ± 0.1V Power Supply Voltage
• 8 internal memory banks
• Programmable CAS Latency: 3,4,5(-37B/-3C/-AC) ;
4,5,6 (-AD)
• Programmable Additive Latency: 0, 1, 2, 3 and 4
• Write Latency = Read Latency -1
• Programmable Burst Length: 4 and 8
• Programmable Sequential / Interleave Burst
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• 4 bit prefetch architecture
•
Packages:
60-Ball BGA for x4 / x8 components
84-Ball BGA for x16 components
Description
The 1Gb Double-Data-Rate-2 (DDR2) DRAMs is a high-
speed CMOS Double Data Rate 2 SDRAM containing
1,073,741,824 bits. It is internally configured as a octal-bank
DRAM.
The 1Gb chip is organized as either 32Mbit x 4 I/O x 8 bank,
16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device.
These synchronous devices achieve high speed double-data-
rate transfer rates of up to 800 Mb/sec/pin for general appli-
cations.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-
output driver, (4) variable data-output impedance adjustment
and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fash-
ion. A 14 bit address bus for x4 and x8 organised compo-
nents and a 13 bit address bus for x16 component is used to
convey row, column, and bank address devices.
These devices operate with a single 1.8V +/- 0.1V power sup-
ply and are available in BGA packages.
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
REV 1.0
10/2007
1
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4CE / NT5TU128M8CE / NT5TU64M16CG
1Gb DDR2 SDRAM
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-
Refresh exit. After VREF has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintained to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select:
All command are masked when CS is registered high. CS provides for external rank
selection on systems with multiple memory ranks. CS is considered part of the command code.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
x8 device, the function of DM or RDQS / RQDS is enabled by EMRS command.
Bank Address Inputs:
BA0, BA1, and BA2 define to which bank an Active, Read, Write or Pre-
charge command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provides the row address for Activate commands and the column address and
Auto Precharge or Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be pre-
charged, the bank is selected by BA0-BA2. The address inputs also provide the op-code during
Mode Register Set commands.
A13 Row address use on x4 and x8 components only.
Data Inputs/Output:
Bi-directional data bus.
Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide dif-
ferential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables
or disables the complementary data strobe signals.
Read Data Strobe:
For x8 components a RDQS and RDQS pair can be enabled via EMRS(1) for
real timming. RDQS and RDQS is not support x4 and x16 components. RDQS and RDQS are
edge-aligned with real data. if enable RDQS and RDQS then DM function will be disabled.
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal
for x4/x8 configuration. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS,
LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to dis-
able ODT.
No Connect:
No internal electrical connection is present.
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
1.8V +/- 0.1V
DQ Ground
DLL Power Supply:
1.8V +/- 0.1V
DLL Ground
Power Supply:
1.8V +/- 0.1V
Ground
SSTL_1.8 reference voltage
CKE
Input
CS
RAS, CAS, WE
DM, LDM, UDM
Input
Input
Input
BA0 - BA2
Input
A0 - A13
Input
DQ
DQS, (DQS)
LDQS, (LDQS),
UDQS,(UDQS)
Input/Output
Input/Output
RDQS, (RDQS)
Input/Output
ODT
Input
NC
V
DDQ
V
SSQ
V
DDL
V
SSDL
V
DD
V
SS
V
REF
REV 1.0
10/2007
4
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
