NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Feature
CAS Latency Frequency
-3C/3CI
Speed Bins
(DDR2-667-CL5)
Parameter
Clock Frequency
Min.
Max.
(DDR2-800-CL5)
Min.
Max.
(DDR2-1066-CL7)
Min.
Max.
(DDR2-1066-CL6)
Min.
Max.
tCK
(Avg.)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
-AC/ACI/ACL
-BE
-BD
Units
125
15
15
60
40
5
3.75
3
-
-
333
-
-
-
70K
8
8
8
-
-
125
12.5
12.5
57.5
40
5
3.75
2.5
2.5
-
400
-
-
-
70K
8
8
8
8
-
125
12.5
12.5
57.5
40
5
3.75
2.5
2.5
1.875
533
-
-
-
70K
8
8
8
8
8
125
11.25
11.25
56.25
40
5
3.75
2.5
1.875
1.875
533
-
-
-
70K
8
8
8
8
8
tRCD
tRP
tRC
tRAS
tCK
(Avg.)
@
CL3
tCK
(Avg.)
@
CL4
tCK
(Avg.)
@
CL5
tCK
(Avg.)
@
CL6
tCK
(Avg.)
@
CL7
*The timing specification of high speed bin is backward compatible with low speed bin
VDD=VDDQ=1.8V ± 0.1V Voltage
JEDEC standard 1.8V I/O (SSTL_18 compatible)
8 internal memory banks
Programmable CAS Latency:
3, 4, 5 (-3C/3CI, -AC/ACI/ACL, -BE, -BD);
6 (-AC/ACI/ACL, -BE, -BD);
7 (-BE, -BD)
Programmable Additive Latency: 0, 1, 2, 3, 4 5
Write Latency = Read Latency -1
Programmable Burst Length:
4 and 8 Programmable Sequential / Interleave Burst
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
4n-bit prefetch architecture
Data-Strobes: Bidirectional, Differential
Support Industrial grade temperature
(–40°C≦TC≦ 95°C; –40°C≦TA≦ +85°C)
Support automotive grade 3 temperature
(–40°C≦TC≦ 95°C; –40°C≦TA≦ +85°C)
1KB page size for x8
2KB page size for x16
Strong and Weak Strength Data-Output Driver
Auto-Refresh and Self-Refresh
Power Saving Power-Down modes
7.8 µs max. Average Periodic Refresh Interval
RoHS Compliance and Halogen Free
AEC-Q100 for NT5TU128M8GE – ACI
PPAP submission for NT5TU128M8GE – ACI
Packages: 60-Ball BGA for x8 components
84-Ball BGA for x16 components
1
REV 2.0
02/2013
©
NANYA TECHNOLOGY CORP
. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Description
The 1giga bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM
containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices
achieve high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance
adjustment and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fashion. A13 bit address bus for x8 organized components and A
12 bit address bus for x16 component is used to convey row, column, and bank address devices.
These devices operate with a single 1.8V ± 0.1V power supply and are available in BGA packages.
2
REV 2.0
02/2013
©
NANYA TECHNOLOGY CORP
. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration
–
60 balls BGA Package (x8)
< TOP View>
See the balls through the package
X8
1
VDD
DQ6
VDDQ
DQ4
VDDL
2
NU,/RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
BA2
BA0
A10/ AP
VSS
A3
A7
VDD
A12
3
VSS
DM/RDQS
VDDQ
DQ3
VSS
WE
BA 1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
3
REV 2.0
02/2013
©
NANYA TECHNOLOGY CORP
. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration
–
84 balls BGA Package (x16)
< TOP View>
See the balls through the package
x 16
1
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
2
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA2
BA0
A10/ AP
VSS
A3
A7
VDD
A12
3
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA 1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
C
K
CK
CS
A0
A4
A8
NC
VSS
VDD
9
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
4
REV 2.0
02/2013
©
NANYA TECHNOLOGY CORP
. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Input / Output Functional Description
Symbol
Type
Function
Clock:
CK and
are differential clock inputs. All address and control input signals are sampled
CK,
Input
on the crossing of the positive edge of CK and negative edge of
.
Output (read) data is
referenced to the crossings of CK and
(both directions of crossing).
Clock Enable:
CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
CKE
Input
Self-Refresh exit. After V
REF
has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, V
REF
must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK,
,
ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select:
All commands are masked when
is registered high.
provides for external rank
Input
selection on systems with multiple memory ranks.
, ,
Input
is considered part of the command code.
Command Inputs:
,
and
(along with
)
define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
DM, LDM, UDM
Input
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
x8 device, the function of DM or RDQS /
is enabled by EMRS command.
Bank Address Inputs:
BA0, BA1, and BA2 define to which bank an Active, Read, Write or
BA0 - BA2
Input
Precharge command is being applied. Bank address also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provides the row address for Activate commands and the column address and
Auto Precharge or Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the
A0 – A13
Input
precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be
precharged, the bank is selected by BA0-BA2. The address inputs also provide the op-code during
Mode Register Set commands.A13 Row address use on x8 components only.
DQ
Input/output
Data Inputs/Output:
Bi-directional data bus.
Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
DQS, ()
the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
LDQS, (),
UDQS,()
differential pair signaling to the system during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals.
Input/output
ended mode or paired with the optional complementary signals
, ,
and
to provide
5
REV 2.0
02/2013
©
NANYA TECHNOLOGY CORP
. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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