DDR2 ECC REGISTERED MINI-DIMM
MODULE CONFIGURATIONS
V/I Part Number
Capacity
VR5JR647218EBP
512MB
VR5JR647218EBS
512MB
VR5JR647218EBW
512MB
VR5JR647218EBZ
512MB
VR5JR647218EBY
512MB
VR5JR287218FBP
1GB
VR5JR287218FBS
1GB
VR5JR287218FBW
1GB
VR5JR287218FBZ
1GB
VR5JR287218FBY
1GB
1
VR5JR287218EBP
1GB
1
VR5JR287218EBS
1GB
1
VR5JR287218EBW
1GB
VR5JR287218EBZ
1
1GB
1
VR5JR287218EBY
1GB
1
VR5JR567218FBP
2GB
1
VR5JR567218FBS
2GB
1
VR5JR567218FBW
2GB
1
VR5JR567218FBZ
2GB
VR5JR567218FBY
1
2GB
1
VR5JR127218FEP
4GB
1
VR5JR127218FES
4GB
1
VR5JR127218FEW
4GB
VR5JR127218GBP
4GB
VR5JR127218GBS
4GB
VR5JR127218GBW
4GB
VR5JR127218GBZ
4GB
VR5JR127218GBY
4GB
Notes:
1. See page 6 for Mechanical Outline.
2. JA = Address Parity
3. JR = No Address Parity
Module
Configuration
64Mx72
64Mx72
64Mx72
64Mx72
64Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
Device
Configuration
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (36)
128M x 8 (36)
128M x 8 (36)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
Device Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
DDP FBGA
DDP FBGA
DDP FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Module
Ranks
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
4
2
2
2
2
2
Performance
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
CAS
Latency
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
Features
•
•
•
•
•
•
•
•
•
•
•
Single 1.8V
±
0.1V Power Supply
Registered inputs with one-clock delay
Burst Length (4, 8)
Burst type (Sequential & Interleave)
Auto & Self-Refresh.
8k/64ms Refresh Period.
Differential CLK (#CLK) input.
On-die termination (ODT)
Off-chip driver (OCD) impedance calibration
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Jxxx7218xxx-LF Revision D1 Created By: Brian Ouellette
Page 1 of 18
DDR2 ECC REGISTERED MINI-DIMM
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
/CK0
TYPE
IN
IN
POLARITY
Positive Edge
Negative
Edge
Active High
DESCRIPTION
Positive line of the differential pair of system clock inputs that drives
input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives
the input to the on-DIMM PLL.
CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers of the SDRAMs. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and
disables decoder when high. When decoder is disabled, new
commands are ignored and previous operations continue. These input
signals also disable all outputs (except CKE and ODT) of the register(s)
on the DIMM when both inputs are high. When both S[0:3] are high, all
register outputs (except CKE, ODT and Chip select) remain in the
previous state.
On-Die Termination control signals
CAS, WE When sampled at the positive rising edge of the clock, /CAS,
/RAS, and /WE define the operation to be executed by the SDRAM.
Reference voltage for SSTL18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide
improved noise immunity
Selects which SDRAM bank of four or eight is activated.
During a Bank Activate command cycle, Address defines the row
address. During a Read or Write command cycle, Address defines the
column address. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2
defines the bank to be precharged. If AP is low, autoprecharge is
disabled. During a Precharge command cycle, AP is used in
conjunction with BA0, BA1,BA2 to control which bank(s) to precharge. If
AP is high, all banks will be precharged regardless of the state of BA0
or BA1. If AP is low, BA0 and BA1 are used to define which bank to
precharge.
Data and Check Bit Input/Output pins
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD
to configure the serial SPD EEPROM address range.
CKE0, CKE1
IN
/S0 ~ /S3
IN
Active Low
ODT0, ODT1
/RAS, /CAS,
/WE
VREF
VDDQ
BA [2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A [An:0]
IN
-
DQ [63:0],
CB [7:0]
DM [8:0]
VDD, VSS
DQS [17:0]
/DQS [17:0]
SA [2:0]
I/O
IN
Supply
I/O
I/O
IN
-
Active High
-
Positive Edge
Negative
Edge
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Jxxx7218xxx-LF Revision D1 Created By: Brian Ouellette
Page 3 of 18
DDR2 ECC REGISTERED MINI-DIMM
PIN FUNCTION DESCRIPTION
SYMBOL
SDA
SCL
VDDSPD
TYPE
I/O
IN
Supply
POLARITY
-
-
-
DESCRIPTION
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. A resistor must be connected from the SDA bus line to
VDDSPD on the system planar to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A
resistor may be connected from the SCL bus time to VDDSPD on the
system planar to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin
at the connector, which supports from 1.7 Volt to 3.6 Volt (nominal 1.8
Volt, 2.5 Volt and 3.3 Volt) operations.
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When low, all register outputs will be driven low and
the PLL clocks to the DRAMs and register(s) will be set to low level (the
PLL will remain synchronized with the input clock)
/RESET
IN
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Jxxx7218xxx-LF Revision D1 Created By: Brian Ouellette
Page 4 of 18
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
