UM8411/8411Z
8 Line ESD/EMI Protection for Color LCD Interfaces
UM8411/8411Z
DFN16 3.3×1.3
General Description
The UM8411/8411Z is a low pass filter array with integrated TVS diodes. It is designed to
suppress unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in
portable electronic equipment. This state-of-the-art device utilizes silicon-avalanche technology
for superior clamping performance and DC electrical characteristics. It has been optimized for
protection of color LCD panels in cellular phones and other portable electronics.
The device consists of eight identical circuits comprised of TVS diodes for ESD protection, and a
RC network for EMI filtering. A series resistor value of 100Ω and a capacitance value of 10pF are
used to achieve 25dB minimum attenuation from 800 MHz to 2.5GHz. The TVS diodes provide
effective suppression of ESD voltages in excess of ±15kV (air discharge) and ±8kV (contact
discharge) per
IEC 61000-4-2, level 4.
The UM8411/8411Z is in a 16-pin, RoHS compliant DFN16 package. It measures 3.3mm ×
1.3mm. The leads are spaced at a pitch of 0.4 mm and are finished with lead-free Ni Pd. The small
package makes it ideal for use in portable electronics such as cell phones, digital still cameras, and
PDAs.
Applications
EMI Filtering and ESD Protection for
Data Lines Wireless Phones
Handheld Products
Notebook Computers
LCD Displays
Features
EMI/RFI Filter with Integrated TVS for ESD
Protection
ESD Protection to IEC 61000-4-2 (ESD)
Level 4, ±15kV (air), ±8kV (contact)
25dB Minimum Attenuation: 800MHz to
2.5GHz
Working Voltage: 5V
Resistor: 100Ω ±15%
Typical Capacitance: 10pF (V
R
= 2.5V)
Solid-state Technology
DFN16 Package: 3.3mm × 1.3 mm
Moisture Sensitivity Level 1
Pin Configurations
Top View
XX: Week Code
UM8411/8411Z
DFN16 3.3×1.3
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UM8411/8411Z
Ordering Information
Part
Number
UM8411
5.0V
UM8411Z
DFN16
L×W=3.3×1.3mm
2
8
8402
Working
Voltage
Packaging Type
Channel
Marking
Code
Shipping Qty
3000pcs /7Inch
Tape & Reel
Tape Size: 8mm
3000pcs /7Inch
Tape & Reel
Tape Size: 12mm
Absolute Maximum Ratings
PARAMETER
Junction Temperature
SteadyíState Power per Resistor @ 25
℃
Operating Temperature Range
Storage Temperature Range
Maximum Lead Temperature for Soldering
SYMBOL
T
J
P
R
T
OP
T
STG
T
L
VALUE
125
328
-40 to 85
-55 to 150
260
UNIT
°C
mW
°C
°C
°C
Electrical Characteristics
PARAMETER
Reverse Stand-Off
Voltage
Reverse Breakdown
Voltage
Reverse Leakage
Current
Total Series Resistance
SYMBOL
V
RWM
V
BR
I
R
R
A
It = 1mA
V
RWM
= 3.3V
85
16
9
100
20
10
150
6.0
7.0
TEST CONDITIONS
MIN
TYP
MAX UNIT
5.0
8.0
100
115
24
12
V
V
nA
Ω
pF
pF
MHz
I
R
=20mA
Each Line
Input to Gnd, Each Line
Total Capacitance
C
d
V
R
= 0V, f = 1MHz
Input to Gnd, Each Line
Total Capacitance
C
d
V
R
= 2.5V, f = 1MHz
Above this frequency,
Cut-Off Frequency
f
3dB
appreciable attenuation
(Notes)
occurs
Notes: 50Ω source and 50Ω load termination.
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UM8411/8411Z
Typical Operating Characteristics
Typical Insertion Loss S21
-5
-10
-35
-30
Analog Crosstalk Curve (S41)
-15
-20
-40
S21 (dB)
-25
-30
-35
-40
-45
1E7
1E8
1E9
S41(dB)
-45
-50
-55
-60
1E7
1E8
1E9
FREQUENCY (Hz)
Frequency(Hz)
Typical Resistance vs. Temperature
104
1.0
Capacitance vs. Reverse Voltage
103
102
0.9
Resistance(ohm)
Cj(Vr)/Cj(Vr=0)
101
100
99
98
97
96
0.8
0.7
0.6
f=1M
0.5
0.4
-40
-20
0
20
40
60
80
0
1
2
3
4
5
Temperature(Celsiur scale)
Reverse Voltage - Vr(V)
ESD Clamping
(+8KV
Contact)
ESD Clamping (-8KV Contact)
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UM8411/8411Z
Applications Information
Device Connection
The UM8411/8411Z is comprised of eight identical circuits each consisting of a low pass filter for
EMI/RFI suppression and dual TVS diodes for ESD protection. The device is in a 16-pin DFN
package. Electrical connection is made to the 16 pins located at the bottom of the device. A center
tab serves as the ground connection. The device has a flow through design for easy layout. All
path lengths should be kept as short as possible to minimize the effects of parasitic inductance in
the board traces. Recommendations for the ground connection are given below.
Ground Connection Recommendation
Parasitic inductance present in the board layout will affect the filtering performance of the device.
As frequency increases, the effect of the inductance becomes more dominant. This effect is given
by Equation 1.
Pin
1-8
7 - 16
Center Tab
Identification
Input Lines
Output Lines
Ground
Equation 1: The Impedance of an Inductor at
Frequency XLF
XLF(L, f ) = 2×л×f ×L
Where:
L= Inductance (H)
f = Frequency (Hz)
Via connections to the ground plane form rectangular wire loops or ground loop inductance as
shown in Figure 2. Ground loop inductance can be reduced by using multiple vias to make the
connection to the ground plane. Bringing the ground plane closer to the signal layer (preferably
the next layer) also reduces ground loop inductance. Multiple vias in the device ground pad will
result in a lower inductive ground loop over two exterior vias. Vias with a diameter d are
separated by a distance y run between layers separated by a distance x. The inductance of the loop
path is given by Equation 2. Thus, decreasing distance x and y will reduce the loop inductance and
result in better high frequency filter characteristics.
Where:
d = Diameter of the wire (in)
x = Length of wire loop (in)
y = Breath of wire loop (in)
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UM8411/8411Z
Figure 3 shows the recommended device layout. The ground pad vias have a diameter of 0.008
inches (0.20 mm) while the two external vias have a diameter of 0.010 inches (0.250mm). The
internal vias are spaced approximately evenly from the center of the pad. The designer may
choose to use more vias with a smaller diameter (such as 0.005 inches or 0.125mm) since
changing the diameter of the via will result in little change in inductance (i.e. the log function in
Equation 2 in highly insensitive to parameter d) .
Figure 3 – Recommended Layout Using Ground Vias
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