UM6411
6 Line ESD/EMI Protection for Color LCD Interfaces
UM6411
DFN12 2.5
X
1.3
General Description
The UM6411 is a low pass filter array with integrated TVS diodes. It is designed to suppress
unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in portable electronic
equipment. This state-of-the-art device utilizes solid-state silicon-avalanche technology for superior
clamping performance and DC electrical characteristics. They have been optimized for protection of
color LCD panels in cellular phones and other portable electronics. The device consists of six
identical circuits comprised of TVS diodes for ESD protection, and a resistor -capacitor network for
EMI/RFI filtering. A series resistor value of 100Ω and a capacitance value of 10pF are used to
achieve 30dB minimum attenuation from 800MHz to 2.5GHz. The TVS diodes provide effective
suppression of ESD voltages in excess of
±15kV
(air discharge) and
±8kV
(contact discharge) per
IEC 61000-4-2, level 4. The UM6411 is in a 12-pin, RoHS compliant, DFN12 2.5mmx1.3mm
package. The leads are spaced at a pitch of 0.4mm and are finished with lead-free Ni Pd. The small
package makes it ideal for use in portable electronics such as cell phones, digital still cameras, and
PDAs.
Applications
Color LCD Protection
Cell Phone CCD Camera Lines
Bottom Connector Cell Phones
Features
Bidirectional EMI/RFI filter with integrated TVS
ESD protection to IEC 61000-4-2 (ESD) Level 4,
±15kV (air), ±8kV (contact)
30dB Minimum Attenuation: 800MHz to 2.5GHz
TVS working voltage: 5V
Resistor: 100Ω±15%
Typical Capacitance: 10pF (VR=2.5V) Protection and
filtering for six lines
Solid-state technology
Pin Configurations
Top View
XX: Weekly Code
UM6411
DFN12 2.5×1.3
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UM6411
Ordering Information
Part Number
UM6411
Working
Voltage
5.0V
Packaging Type
DFN12
Channel
6
Marking Code
6411
Shipping Qty
3000/7Inchs
Tape & Reel
Absolute Maximum Ratings
PARAMETER
Junction Temperature
Steady-State Power per Resistor @ 25℃
Operating Temperature Range
Storage Temperature Range
Maximum Lead Temperature for Soldering
SYMBOL
T
J
P
R
T
OP
T
STG
T
L
VALUE
125
328
-40 to 85
-55 to 150
260
UNITS
°C
mW
°C
°C
°C
Electrical Characteristics
PARAMETER
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Total Series Resistance
Total Capacitance
Total Capacitance
Cut-Off Frequency (Notes)
SYMBOL
V
RWM
V
BR
I
R
R
A
C
d
C
d
f
3dB
It = 1mA
V
RWM
= 3.0V
I
R
=20mA
Each Line
Input to Gnd, Each Line
V
R
= 0V, f = 1MHz
Input to Gnd, Each Line
V
R
= 2.5V, f = 1MHz
Above this frequency,
appreciable attenuation
occurs
6
7
CONDITIONS
MIN
TYP
MAX
5
8
0.5
85
16
9
100
20
10
150
115
24
12
UNITS
V
V
μA
Ω
pF
pF
MHz
Notes: 50Ω source and 50Ω load termination.
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UM6411
Typical Operating Characteristics
Typical Insertion Loss S21
-5
-10
-35
-30
Analog Crosstalk Curve (S41)
-15
-20
-40
S21 (dB)
-25
-30
-35
-40
-45
1E7
1E8
1E9
S41(dB)
-45
-50
-55
-60
1E7
1E8
1E9
FREQUENCY (Hz)
Frequency(Hz)
Typical Resistance vs. Temperature
104
1.0
Capacitance vs. Reverse Voltage
103
102
0.9
Resistance(ohm)
Cj(Vr)/Cj(Vr=0)
101
100
99
98
97
96
0.8
0.7
0.6
f=1M
0.5
0.4
-40
-20
0
20
40
60
80
0
1
2
3
4
5
Temperature(Celsiur scale)
Reverse Voltage - Vr(V)
ESD Clamping (+8kV Contact)
ESD Clamping (-8kV Contact)
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UM6411
Applications Information
Device Connection
The UM6411 is comprised of six identical circuits each consisting of a low pass filter for EMI/RFI
suppression and dual TVS diodes for ESD protection. The device is in a 12-pin DFN package.
Electrical connection is made to the 12 pins located at the bottom of the device. A center tab serves as
the ground connection. The device has a flow through design for easy layout. Pin connections are
noted in Figure 1. All path lengths should be kept as short as possible to minimize the effects of
parasitic inductance in the board traces. Recommendations for the ground connection are given
below.
Ground Connection Recommendation
Parasitic inductance present in the board layout will affect the filtering performance of the device. As
frequency increases, the effect of the inductance becomes more dominant. This effect is given by
Equation 1.
Pin
1-6
7 - 12
Center Tab
Identification
Input Lines
Output Lines
Ground
Equation 1: The Impedance of an Inductor at Frequency XLF
XLF(L,f ) = 2×л×f ×L
Where:
L= Inductance (H)
f = Frequency (Hz)
Via connections to the ground plane form rectangular wire loops or ground loop inductance as shown
in Figure 2. Ground loop inductance can be reduced by using multiple vias to make the connection to
the ground plane. Bringing the ground plane closer to the signal layer (preferably the next layer) also
reduces ground loop inductance. Multiple vias in the device ground pad will result in a lower
inductive ground loop over two exterior vias. Vias with a diameter d are separated by a distance y run
between layers separated by a distance x. The inductance of the loop path is given by Equation 2.
Thus, decreasing distance x and y will reduce the loop inductance and result in better high frequency
filter characteristics.
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UM6411
Where:
d = Diameter of the wire (in)
x = Length of wire loop (in)
y = Breath of wire loop (in)
Figure 3 shows the recommended device layout. The ground pad vias have a diameter of 0.008 inches (0.20 mm)
while the two external vias have a diameter of 0.010 inches (0.250mm). The internal vias are spaced
approximately evenly from the center of the pad. The designer may choose to use more vias with a smaller
diameter (such as 0.005 inches or 0.125mm) since changing the diameter of the via will result in little change in
inductance (i.e. the log function in Equation 2 in highly insensitive to parameter d) .
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