DDR3
ECC ADDRESS PARITY VLP DIMM
VR7VAxx7298xxx
Module Configuration
VMS Part Number
VR7VA287298FBZ
VR7VA287298FBA
VR7VA287298FBB
VR7VA287298FBC
VR7VA287298FBD
VR7VA287298FBE
VR7VA567298GBZ
VR7VA567298GBA
VR7VA567298GBB
VR7VA567298GBC
VR7VA567298GBD
VR7VA567298GBE
VR7VA567298FBZ
VR7VA567298FBA
VR7VA567298FBB
VR7VA567298FBC
VR7VA567298FBD
VR7VA567298FBE
VR7VA127298GBZ
VR7VA127298GBA
VR7VA127298GBB
VR7VA127298GBC
VR7VA127298GBD
VR7VA127298GBE
Capacity
1GB
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
4GB
Module
Configuration
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
Device Configuration
128Mx8 (9)
128Mx8 (9)
128Mx8 (9)
128Mx8 (9)
128Mx8 (9)
128Mx8 (9)
256Mx8 (9)
256Mx8 (9)
256Mx8 (9)
256Mx8 (9)
256Mx8 (9)
256Mx8 (9)
128Mx8 (18)
128Mx8 (18)
128Mx8 (18)
128Mx8 (18)
128Mx8 (18)
128Mx8 (18)
256Mx8 (18)
256Mx8 (18)
256Mx8 (18)
256Mx8 (18)
256Mx8 (18)
256Mx8 (18)
Device Package
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
TFBGA
Module
Ranks
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
Performance
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
CAS Latency
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
Features
•
•
•
•
•
•
•
•
JEDEC standard 1.35V (1.283V to 1.45V) Power Supply
o
VDD = 1.35V (1.283V to 1.45V)
o
VDDSPD = +3.0V to +3.6V
240-pin Registered Dual-In-Line Memory Module with
parity bit for address and control bus.
8 Internal Banks.
Programmable CAS Latency: 6, 7, 8, 9, 10
Programmable CAS Write Latency (CWL).
Programmable Additive Latency (Posted CAS).
Fixed burst chop (BC) of 4 and burst length (BL) of 8 via
the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
•
•
•
•
•
•
•
•
•
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
Serial Presence Detect with EEPROM.
On-DIMM Thermal Sensor.
Asynchronous Reset.
VLP RDIMM dimensions: 133.35 mm x 18.75 mm.
RoHS Compliant* (see last page)
Nomenclature
Module Standard
PC3-6400
PC3 -8500
PC3-10600
PC3-12800
SDRAM Standard
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Clock
400MHz
533MHz
667MHz
800MHz
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7VAxx7298xxx Revision A Created By: Brian Ouellette
Page 1 of 22
DDR3
ECC ADDRESS PARITY VLP DIMM
VR7VAxx7298xxx
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Front
Pin
Side
VREFDQ 121
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
122
123
124
125
Back
Side
VSS
DQ4
DQ5
VSS
DQS9, TDQS9
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Side
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
VTT
VTT
CKE0
VDD
BA2
Err_Out#
VDD
A11
A7
VDD
A5
A4
VDD
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
KEY
169
170
171
172
173
174
175
176
177
178
179
180
Back
Side
VSS
DQS12,
TDQS12
DQS12#,
TDQS12#
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DQS17,
TDQS17
DQS17#,
TDQS17#
VSS
CB6
CB7
VSS
NC(TEST)
RESET#
CKE1
VDD
A15
A14
VDD
A12 / BC#
A9
VDD
A8
A6
VDD
A3
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
Side
A2
VDD
CK1
CK1#
VDD
VDD
Pin
181
182
183
184
185
186
Back
Side
A1
VDD
VDD
CK0
CK0#
VDD
EVENT#,
NC
A0
VDD
BA1
VDD
RAS#
S0#
VDD
ODT0
A13
VDD
S3#
VSS
DQ36
DQ37
VSS
DQS13,
TDQS13
DQS13#,
TDQS13#
VSS
DQ38
DQ39
VSS
DQ44
DQ45
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
Side
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SA0
SCL
SA2
VTT
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
Side
VSS
DQS14,
TDQS14
DQS14#,
TDQS14#
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DQS15,
TDQS15
DQS15#,
TDQS15#
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS16,
TDQS16
DQS16#,
TDQS16#
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
SDA
VSS
VTT
126 DQS9#, TDQS9#
127
128
129
130
131
132
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VREFCA 187
Par_In 188
VDD
189
A10 / AP 190
BA0
VDD
WE#
CAS#
VDD
S1#
ODT1
VDD
S2#
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
133
VSS
134 DQS10, TDQS10
DQS10#,
135
TDQS10#
136
VSS
137
DQ14
138
DQ15
139
VSS
140
141
142
DQ20
DQ21
VSS
143 DQS11, TDQS11
144
145
146
147
148
149
150
DQS11#,
TDQS11#
VSS
DQ22
DQ23
VSS
DQ28
DQ29
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7VAxx7298xxx Revision A Created By: Brian Ouellette
Page 2 of 22
DDR3
ECC ADDRESS PARITY VLP DIMM
VR7VAxx7298xxx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
/CK0
CKE[1:0]
TYPE
IN
IN
IN
POLARITY
Positive Edge
Negative Edge
Active High
DESCRIPTION
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM
Clock
Driver.
Negative line of the differential pair of system clock inputs that drives the input to the on-
DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations
continue. These input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register
outputs (except CKE, ODT and Chip select) remain in the previous state. For modules
supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1,
Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also
determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the
memory array in the respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also
utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address
inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register A11=1
in MR1, DRAM will enable the same termination resistance function on TDQS, TDQS#
that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1, DM,
TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs must
disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pullup.
S[3:0]#
IN
Active Low
ODT[1:0]
RAS#, CAS#,
WE#
VREFDQ
VREFCA
BA[2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A[15:13,
12/BC,11,
10/AP,9:0]
DQ [63:0],
CB [7:0]
VDD, VSS
DM [8:0]
VDD, VSS
VTT
DQS[17:0]
DQS [17:0]#
TDQS[17:9],
TDQS[17:9]#
SA [2:0]
SDA
IN
-
I/O
Supply
IN
Supply
Supply
I/O
I/O
OUT
-
-
Active High
Positive Edge
Negative Edge
IN
I/O
-
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7VAxx7298xxx Revision A Created By: Brian Ouellette
Page 3 of 22
DDR3
ECC ADDRESS PARITY VLP DIMM
VR7VAxx7298xxx
PIN FUNCTION DESCRIPTION
SYMBOL
SCL
EVENT#
VDDSPD
RESET#
Par_In
Err_Out#
TEST
TYPE
IN
OUT
(open drain)
Supply
IN
IN
OUT
POLARITY
-
Active Low
-
DESCRIPTION
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and
register(s) will be set to low level (the PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7VAxx7298xxx Revision A Created By: Brian Ouellette
Page 4 of 22
DDR3
ECC ADDRESS PARITY VLP DIMM
VR7VAxx7298xxx
MECHANICAL OUTLINE
Dimensions are in inches. (Tolerance is +/- 0.005, unless otherwise stated.)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7VAxx7298xxx Revision A Created By: Brian Ouellette
Page 5 of 22
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