1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Feature
1.5V ± 0.075V (JEDEC Standard Power Supply)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK,
)
Programmable
Latency: 5, 6, 7, 8, 9
Programmable Additive Latency: 0, CL-1, CL-2
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8 bit prefetch architecture
Output Driver Impedance Control
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
Partial Array Self-Refresh
RoHS Compliance
Packages:
78-Ball BGA for x4 & x8 components
96-Ball BGA for x16 components
Description
The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 1,073,741,824 bits. It is
internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices
achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
falling). All
I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.75V power supply and are available in BGA packages.
1
REV 1.2
01 / 2009
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Input / Output Functional Description
Symbol
Type
Function
Clock:
CK and
are differential clock inputs. All address and control input signals are sampled on
CK,
Input
the crossing of the positive edge of CK and negative edge of
.
Clock Enable:
CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
CKE
Input
Self-Refresh exit. After V
REF
has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit,
V
REF
must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK,
,
ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select:
All commands are masked when
is registered high.
provides for external rank
Input
selection on systems with multiple memory ranks.
, ,
Input
is considered part of the command code.
Command Inputs:
,
and
(along with
)
define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges
DM, (DMU, DML)
Input
of DQS. For x8 device, the function of DM or TDQS /
is enabled by Mode Register A11
setting in MR1
Bank Address Inputs:
BA0, BA1, and BA2 define to which bank an Active, Read, Write or
BA0 - BA2
Input
Precharge command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Address Inputs:
Provide the row address for Activate commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
A0 – A13
Input
(A10/AP and A12/BC# have additional function as below. The address inputs also provide the
op-code during Mode Register Set commands. A13 did not apply on x16 device.
Burst Chop:
A12/ is sampled during Read and Write commands to determine if burst chop (on
A12 / BC#
Input
the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
DQ
Input/output
Data Inputs/Output:
Bi-directional data bus.
Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, DQSL corresponds to the data on DQL0 - DQL7; DQSU corresponds to
DQU, DQL
the data on DQU0-DQU7. The data strobes DQS, DQSL, DQSU are paired with differential signals
DQS, ()
Input/output
DQSL, (),
reads and writes. DDR3 SDRAM supports differential data strobe only and does not support
DQSU,()
single-ended.
, , ,
respectively, to provide differential pair signaling to the system during both
5
REV 1.2
01 / 2009
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