1Gb DDR3 SDRAM C-Die
NT5CB256M4CN / NT5CB128M8CN
Feature
1.5V ± 0.075V (JEDEC Standard Power Supply)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK,
)
Programmable
Latency: 5, 6, 7, 8, 9, 10
Programmable Additive Latency: 0, CL-1, CL-2
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8 bit prefetch architecture
Output Driver Impedance Control
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
RoHS Compliance and Halogen free
Packages:
78-Ball BGA for x4 & x8 components
Description
The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing
1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8, or 16Mbit x 8 I/O x 8 bank device. These synchronous devices achieve
high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks
(CK rising and
falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
1
REV 1.0
12 / 2009
1Gb DDR3 SDRAM C-Die
NT5CB256M4CN / NT5CB128M8CN
Pin Configuration
–
78 balls BGA Package (x4)
< TOP View>
See the balls through the
package
x4
1
VSS
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
2
VDD
VSSQ
DQ2
NC
VDDQ
VSS
VDD
BA0
A3
A5
A7
3
NC
DQ0
DQS
NC
BA2
A0
A2
A9
A13
A
B
C
D
E
F
G
H
J
K
L
M
N
7
NC
DM
DQ1
VDD
NC
CK
A10/AP
NC
A12/
A1
A11
NC
8
VSS
VSSQ
DQ3
VSS
NC
VSS
VDD
ZQ
VERFCA
BA1
A4
A6
A8
9
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
2
REV 1.0
12 / 2009
1Gb DDR3 SDRAM C-Die
NT5CB256M4CN / NT5CB128M8CN
Pin Configuration
–
78 balls BGA Package (x8)
< TOP View>
See the balls through the package
x 8
1
VSS
2
VDD
3
NC
A
7
NU/
8
VSS
9
VDD
VSS
VSSQ
DQ0
B
DM/TDQS
VSSQ
VDDQ
VDDQ
DQ2
DQS
C
DQ1
DQ3
VSSQ
VSSQ
DQ6
D
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
E
DQ7
DQ5
VDDQ
NC
ODT
VSS
F
CK
VSS
NC
VDD
G
VDD
CKE
NC
H
A10/AP
ZQ
NC
VSS
BA0
BA2
J
NC
VERFCA
VSS
VDD
A3
A0
K
A12/
BA1
VDD
VSS
A 5
A2
L
A1
A4
VSS
VDD
A7
A9
M
A11
A6
VDD
VSS
A13
N
NC
A8
VSS
3
REV 1.0
12 / 2009
1Gb DDR3 SDRAM C-Die
NT5CB256M4CN / NT5CB128M8CN
Input / Output Functional Description
Symbol
Type
Function
Clock:
CK and
are differential clock inputs. All address and control input signals are sampled on
CK,
Input
the crossing of the positive edge of CK and negative edge of
.
Clock Enable:
CKE high activates, and CKE low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh
operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit.
CKE
Input
After V
REF
has become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver. For proper self-refresh entry and exit, V
REF
must maintain
to this input. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK,
,
ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
Chip Select:
All commands are masked when
is registered high.
provides for external rank
Input
selection on systems with multiple memory ranks.
, ,
Input
is considered part of the command code.
Command Inputs:
,
and
(along with
)
define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges
DM, (DMU, DML)
Input
of DQS. For x8 device, the function of DM or TDQS /
is enabled by Mode Register A11 setting
in MR1
Bank Address Inputs:
BA0, BA1, and BA2 define to which bank an Active, Read, Write or
BA0 - BA2
Input
Precharge command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Address Inputs:
Provide the row address for Activate commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
A0 – A13
Input
(A10/AP and A12/ have additional function as below. The address inputs also provide the op-code
during Mode Register Set commands.
Burst Chop:
A12/ is sampled during Read and Write commands to determine if burst chop (on
A12 /
Input
the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
DQ
Input/output
Data Inputs/Output:
Bi-directional data bus.
Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered
DQL,
DQU,
DQS,(),
DQSL,(),
DQSU,(),
Input/output
with write data. The data strobes DQS, DQSL, DQSU are paired with differential signals
, ,
,
respectively, to provide differential pair signaling to the system during both reads and writes.
DDR3 SDRAM supports differential data strobe only and does not support single-ended.
4
REV 1.0
12 / 2009
1Gb DDR3 SDRAM C-Die
NT5CB256M4CN / NT5CB128M8CN
Symbol
Type
Function
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR3
SDRAM. When enabled, ODT is applied to each DQ, DQS,
and DM/TDQS, NU/ (when
ODT
Input
TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be
ignored if MR1and MR2 are programmed to disable RTT.
Active Low Asynchronous Reset:
Reset is active when
is LOW, and inactive when
Input
is HIGH.
must be HIGH during normal operation.
is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V
NC
V
DDQ
V
DD
V
SSQ
V
ss
V
REFCA
V
REFDQ
ZQ
Supply
Supply
Supply
Supply
Supply
Supply
Supply
No Connect:
No internal electrical connection is present.
DQ Power Supply:
Power Supply:
DQ Ground
Ground
Reference voltage for CA
Reference voltage for DQ
Reference pin for ZQ calibration.
1.5V ± 0.075V
1.5V ± 0.075V
Note: Input only pins (BA0-BA2, A0-A13,
, , , ,
CKE, ODT, and
)
do not supply termination.
DDR3 SDRAM Addressing
Configuration
# of Bank
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size
NT5CB256M4CN
8
BA0 – BA2
A10 / AP
A12 /
A0 – A13
A0 – A9, A11
2KB
NT5CB128M8CN
8
BA0 – BA2
A10 / AP
A12 /
A0 – A13
A0 – A9
1KB
Note:
Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command is
registered. Page size is per bank, calculated as follows:
Page size = 2
COLBITS
* ORG / 8
COLBITS = the number of column address bits
ORG = the number of I/O (DQ) bits
5
REV 1.0
12 / 2009
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