N2DS51280CS
512Mb DDR SDRAM C-Die
Features
• DDR 512M bit, Die C, based on 90nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• V
DD
= V
DDQ
= 2.6V
±
0.1V (DDR400)
• V
DD
= V
DDQ
= 2.5V
±
0.2V (DDR333)
• RoHS compliance
Description
Die C of 512Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 90 nm design process.
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a
2n
prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 512Mb
DDR SDRAM effectively consists of a single
2n-bit
wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
REV 1.0
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NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
N2DS51280CS
512Mb DDR SDRAM C-Die
Ordering Information (Green)
Org.
Part Number
N2DS51280CS-6K
N2DS51280CS-5T
Package
Speed
Clock (MHz)
166
200
CL-t
RCD
-t
RP
2.5-3-3
3-3-3
Comments
DDR333
DDR400
64M x 8
TSOP(II)
REV 1.0
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NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
N2DS51280CS
512Mb DDR SDRAM C-Die
Pin Configuration - 66 TSOPII (x8)
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
66-pin Plastic TSOP-II 400mil
64Mb x 8
Column Address Table
Organization
64Mb x 8
Column Address
A0 - A9, A11
Row Address
A0 - A12
*DM is internally loaded to match DQ and DQS identically
.
REV 1.0
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NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
N2DS51280CS
512Mb DDR SDRAM C-Die
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin.
Chip Select:
All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
Data Input/Output:
Data bus.
Data Strobe:
Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.
No Connect:
No internal electrical connection is present.
Not Useable:Electrical
connection is present. Should not be connected at second level of assem-
bly.
DQ Power Supply:
2.6V
±
0.1V (DDR400); 2.5V
±
0.2V (DDR333)
DQ Ground
Power Supply:
2.6V
±
0.1V (DDR400); 2.5V
±
0.2V (DDR333)
Ground
SSTL_2 reference voltage
CKE
Input
CS
RAS, CAS, WE
DM
Input
Input
Input
BA0, BA1
Input
A0 - A12
Input
DQ
DQS
NC
NU
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Input/Output
Input/Output
-
-
Supply
Supply
Supply
Supply
Supply
REV 1.0
June 2006
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NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
N2DS51280CS
512Mb DDR SDRAM C-Die
Block Diagram (64Mb x 8)
Control Logic
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Bank1
Row-Address MUX
Bank0
Row-Address Latch
& Decoder
Bank2
Bank3
CK, CK
DLL
Mode
Registers
13
13
8192
Read Latch
Refresh Counter 13
8
8
MUX
Sense Amplifiers
16384
16
8
DQS
Generator
1
Bank Control Logic
Drivers
15
Bank0
Memory
Array
(8192 x 1024 x 16)
Data
Address Register
2
1024
(x16)
Column
Decoder
10
11
Column-Address
Counter/Latch
1
COL0
8
16
8
clk
clk
out in Data
CK,
CK
COL0
2
8
8
8
1
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
REV 1.0
June 2006
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©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Receivers
A0-A12,
BA0, BA1
2
15
I/O Gating
DM Mask Logic
COL0
16
16
Write
FIFO
&
Drivers
Input
Register
1
Mask 1
1
1
DQS
1
DQ0-DQ7,
DM
DQS
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