NT5TU16M16AG
NT5TU16M16AF
256Mb DDR2 SDRAM
Features
CAS Latency and Frequency
Speed Sorts
Bin
(CL-tRCD-TRP)
max. Clock
Frequency
Data Rate
CAS Latency
t
RCD
t
RP
t
RC
-37B
DDR2
-533
-3C
DDR2
-667
-25D
DDR2
-800
• Programmable Additive Latency: 0, 1, 2, 3, and 4
• Write Latency = Read Latency -1
Units
tck
MHz
Mb/s/pin
tck
ns
ns
ns
• Programmable Burst Length: 4 and 8
• Programmable Sequential / Interleave Burst
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• 4 bit prefetch architecture
• 1KB page size
• Data-Strobes: Bidirectional, Differential
• Strong and Weak Strength Data-Output Driver
• Auto-Refresh and Self-Refresh
• Power Saving Power-Down modes
• 7.8 µs max. Average Periodic Refresh Interval
• Packages:
84-Ball BGA
4-4-4
266
533
4
15
15
60
5-5-5
333
667
5
15
15
60
6-6-6
400
800
6
15
15
60
• 1.8V ± 0.1V Power Supply Voltage
• 4 internal memory banks
• Programmable CAS Latency: 4, 5, and 6
Description
The 256Mb Double-Data-Rate-2 (DDR2) DRAMs is a high-
speed CMOS Double Data Rate 2 SDRAM. It is internally
configured as a Quad-bank DRAM.
The 256Mb chip is organized as 4Mbit x 16 I/O x 4 bank
device. These synchronous devices achieve high speed dou-
ble-data-rate transfer rates of up to 800 Mb/sec/pin for gen-
eral applications.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-
output driver, (4) variable data-output impedance adjustment
and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
LDQS / UDQS or differential LDQS / UDQS pair in a source
synchronous fashion. A 12 bit address bus for x16 organised
components is used to convey row, column, and bank
address devices.
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
These devices operate with a single 1.8V +/- 0.1V power sup-
ply and are available in BGA packages.
REV 1.4
12/2007
1
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU16M16AG
NT5TU16M16AF
256Mb DDR2 SDRAM
Pin Configuration - 84 Balls BGA Package (x16)
<Top View >
See the balls through the package.
x 16
1
2
3
7
8
9
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
NC
BA0
A10 / AP
VDD
VSS
A3
A7
VSS
VDD
A12
REV 1.4
12/2007
2
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU16M16AG
NT5TU16M16AF
256Mb DDR2 SDRAM
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-
Refresh exit. After VREF has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintained to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select:
All command are masked when CS is registered high. CS provides for external rank
selection on systems with multiple memory ranks. CS is considered part of the command code.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
LDM / UDM is an input mask signal for write data. Input data is masked when
LDM / UDM is sampled high coincident with that input data during a Write access. LDM / UDM is
sampled on both edges of LDQS
/
UDQS. Although LDM / UDM pins are input only, the LDM /
UDM loading matches the DQ and LDQS
/
UDQS loading.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provides the row address for Activate commands and the column address and
Auto Precharge or Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be pre-
charged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code
during Mode Register Set commands.
Data Inputs/Output:
Bi-directional data bus.
Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
the data on DQ8-DQ15. The data strobes LDQS, and UDQS may be used in single ended mode
or paired with the optional complementary signals LDQS, UDQS to provide differential pair signal-
ing to the system during both reads and writes. An EMRS(1) control bit enables or disables the
complementary data strobe signals.
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM
and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to disable ODT.
No Connect:
No internal electrical connection is present.
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
1.8V +/- 0.1V
DQ Ground
DLL Power Supply:
1.8V +/- 0.1V
DLL Ground
Power Supply:
1.8V +/- 0.1V
Ground
SSTL_1.8 reference voltage
CKE
Input
CS
RAS, CAS, WE
LDM, UDM
Input
Input
Input
BA0 - BA1
Input
A0 - A12
Input
DQx,
LDQS, (LDQS),
UDQS,(UDQS)
Input/Output
Input/Output
ODT
NC
V
DDQ
V
SSQ
V
DDL
V
SSDL
V
DD
V
SS
V
REF
Input
REV 1.4
12/2007
3
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU16M16AG
NT5TU16M16AF
256Mb DDR2 SDRAM
Ordering Information
Org.
Part Number
NT5TU16M16AG-37B
Package
Speed
Clock (MHz)
266
333
CL-t
RCD
-t
RP
4-4-4
5-5-5
6-6-6
4-4-4
5-5-5
6-6-6
4-4-4
5-5-5
16M x 16
NT5TU16M16AG-3C
NT5TU16M16AG-25D
NT5TU16M16AG-37BI
84-Ball BGA
Lead-Free
400
266
333
400
16M x 16
NT5TU16M16AG-3CI
NT5TU16M16AG-25DI
16M x 16
NT5TU16M16AF-37B
NT5TU16M16AF-3C
84-Ball BGA
Leaded
266
333
REV 1.4
12/2007
4
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU16M16AG
NT5TU16M16AF
256Mb DDR2 SDRAM
Functional Description
The 256Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory. The 256Mb DDR SDRAM is internally
configured as a octal-bank DRAM.
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the
burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is
followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the
bank and row to be accesses (BA0 & BA1 select the banks, A0-A12 select the row, and A0-A8 select the column). The address
bits registered coincident with the Read or Write command are used to select the starting column location for the burst access
and to determine if the Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering
device initialization, register definition, command description and device operation.
Power-up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified
may result in undefined operation.
The following sequence is required for POWER UP and Initialization.
1. Either one of the following sequence is required for Power-up.
While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be unde-
fined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and
during the VDD voltage ramp up, IVDD-VDDQI<=0.3 volts. Once the ramping of the supply voltages is complete (when
VDDQ crosses VDDQ min), the supply voltage specifications in Recommanded DC operating conditions table.
-
VDD,VDDL, and VDDQ are driven from a signle power converter output, AND
- VTT is limited to 0.95V max, AND
- vref tracks VDDQ/2, Vref must be within +/-300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ>=VREF must be met at all times.
While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be unde-
fined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During
the ramping of the supply voltages, VDD>=VDDL>=VDDQ must be maintained and is applicable to both AC and DC levels
until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the
supply voltages is complete, the supply voltage specifications provided in Recommanded DC operating conditions table.
- Apply VDD/VDDL before or at the same time as VDDQ.
- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin.
- Apply VDDQ before or at the same time as VTT.
- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ
must be no greater than 500ms.
(Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.
- Vref must track VDDQ/2, Vref must be within +/-300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ >= VREF must be met at all time.
- Apply VTT.
2. Start clock (CK, CK) and maintain stable condition.
3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and
maximum values as stated in Recommanded DC operating conditions table, and stable clock, then apply NOP or Deselect
& take CKE HIGH.
4. Waiting minimum of 400ns then issue precharge all command. NOP or Deselect applied during 400ns period.
5. Issue an EMRS command to EMR(2). (Provide LOW to BA0, and HIGH to BA1).
6. Issue an EMRS command to EMR(3). (Provide HIGH to BA0 and BA1).
REV 1.4
12/2007
5
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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