NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
Features
•
High Performance:
Maximum Operating Speed
CAS
Latency
2
3
PC166
(6K)
10
6
PC133
(75B)
10
7.5
ns
ns
•
•
•
•
•
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BA0/BA1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8 or full page
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
Random Column Address every CK (1-N Rule)
Single Power Supply, either 3.3V or 2.5V
LVTTL compatible
Packages: TSOP-Type II
Lead-free & Halogen-free product available
Description
The NT5SV8M16DS, NT5SV8M16DT, NT5SE8M16DS and
NT5EV8M16DT are four-bank Synchronous DRAMs orga-
nized as 2Mbit x 16 I/O x 4 Bank. These synchronous
devices achieve high-speed data transfer rates of up to
166MHz by employing a pipeline chip architecture that syn-
chronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve addresses (A0-A11) and two bank
select addresses (BA0, BA1) are strobed with RAS. Nine col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
REV 1.0
May 9, 2005
1
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
Ordering Information
Organization
Part Number
Package
400mil 54-PIN
TSOP II
Lead-Free
400mil 54-PIN
TSOP II
400mil 54-PIN
TSOP II
Lead-Free
400mil 54-PIN
TSOP II
400mil 54-PIN
TSOP II
Lead-Free
400mil 54-PIN
TSOP II
400mil 54-PIN
TSOP II
Lead-Free
400mil 54 PIN
TSOP II
Lead free packaging
166MHz-3-3-3
Power
Speed Grade
Clock Frequency
CL-t
RCD
-t
RP
Notes
NT5SV8M16DS-6K
Lead free packaging
166MHz-3-3-3
NT5SV8M16DT-6K
8M x 16
NT5SV8M16DS-75B
3.3V
Lead free packaging
133MHz-3-3-3
NT5SV8M16DT-75B
NT5SE8M16DS-6K
NT5SE8M16DT-6K
8M x 16
NT5SE8M16DS-75B
2.5V
Lead free packaging
133MHz-3-3-3
NT5SE8M16DT-75B
CL = CAS Latency
Lead-free products are also halogen-free
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
REV 1.0
May 9, 2005
2
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
Pin Configuration - 54 pins 400 mill TSOPII Package
<Top View >
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
54-pin Plastic TSOP(II) 400 mil
REV 1.0
May 9, 2005
3
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
Pin Description
CK
CKE (CKE0, CKE1)
CS
RAS
CAS
WE
BA1, BA0
A0 - A11
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
Input/Output Functional Description
Symbol
CK
CKE, CKE0,
CKE1
CS
RAS, CAS, WE
BA1, BA0
Type
Input
Input
Input
Input
Input
Polarity
Positive
Edge
Active High
Active Low
Active Low
—
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8), when sam-
pled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10
is low, then BA0 and BA1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
A0 - A11
Input
—
DQ0 - DQ15
Input-
Output
—
DQM
LDQM
UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has
a latency of zero and operates as a word mask by allowing input data to be written if it is low but
blocks the write operation if DQM is high.
—
—
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
V
DD
, V
SS
V
DDQ
V
SSQ
Supply
Supply
REV 1.0
May 9, 2005
4
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
Block Diagram
CKE
CKE Buffer
Row Decoder
Column Decoder
Column Decoder
Cell Array
Memory Bank 0
Row Decoder
Cell Array
Memory Bank 1
CK
CK Buffer
Sense Amplifiers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
BA1
BA0
A10
Sense Amplifiers
Data Input/Output Buffers
DQM
Column Decoder
Cell Array
Memory Bank 3
Sense Amplifiers
Address Buffers (15)
Control Signal
Generator
Data Control Circuitry
DQ
0
DQ
X
Refresh
Counter
Column
Address
Counter
Mode Register
Column Decoder
Row Decoder
CS
RAS
CAS
WE
Command Decoder
Cell Array
Memory Bank 2
Sense Amplifiers
Cell Array, per bank, for 4Mb x 16 DQ: 4096 Row x 512 Col x 16 DQ (DQ0-DQ15).
REV 1.0
May 9, 2005
5
©
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Row Decoder
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