UTRON
Rev. 1.1
REVISION HISTORY
REVISION
Rev. 0.9
Rev. 1.0
DESCRIPTION
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
Original.
1. The Operating Temperature is revised from Industrial temperature to
Extended temperature
：
-20
℃
~80
℃
2. The symbols CE1#,OE# and WE# are revised as CE1 , OE and
WE
Add order information for lead free product
DATE
Jan.2001
Jun 18,2001
May 15,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
1
UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT621024(E) is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT621024(E) is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT621024(E) operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 2µA (typical) L-version
1µA (typical) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
OperatingTemperature :
Extended : -20
℃
~80
℃
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
32-pin 8mmx13.4mm STSOP
PIN CONFIGURATION
NC
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
FUNCTIONAL BLOCK DIAGRAM
1024 X 1024
MEMORY
ARRAY
A14
A12
A7
A6
A5
A4
A3
UT621024(E)
A13
A8
A9
A11
OE
A0-A16
DECODER
Vcc
Vss
A2
A1
A0
I/O1
I/O2
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
I/O3
Vss
PDIP / SOP
A11
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
OE
A10
CE
CE2
OE
A8
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
CONTROL
CIRCUIT
A13
WE
WE
CE2
A15
Vcc
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
NC
A16
A14
A12
A7
A6
A5
A4
UT621024(E)
25
24
23
22
21
20
19
18
17
TSOP-I/STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
2
UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to Vss
Operating Temperature
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
solder
RATING
-0.5 to +7.0
-20 to +80
-65 to +150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High -Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,
I
SB1
I
SB
,
I
SB1
I
CC
I
CC
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= -20
℃
to 80
℃
)
PARAMETER
SYMBOL TEST CONDITION
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
IL
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current I
OL
V
SS
≦
V
I/O
≦
V
CC
CE =V
IH
or CE2 = V
IL
or
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
V
OH
V
OL
I
CC
OE
= V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
Min.Cycle, 100% Duty,
CE =V
IL
, CE2 = V
IH
,
I
I/O
= 0mA
Cycle time = 1µs, 100% Duty,
.
CE
≦
0.2V,CE2
≧
V
CC
-0.2V,
I
I/O
= 0Ma
CE =V
IH
or CE2 = V
IL
CE
≧
V
CC
-0.2V or
.CE2
≦
0.2V
-L
- LL
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. Those parameters are for reference only under 50
MIN.
2.2
- 0.5
-1
-1
2.4
-
-35
-55
-70
-
-
-
-
-
-
-
TYP.
-
-
-
-
-
-
60
50
40
-
-
2
1
MAX.
V
CC
+0.5
0.8
1
1
-
0.4
100
85
70
10
3
200
4
40*
100
4
15*
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
µA
I
CC1
Standby Power
Supply Current
I
SB
I
SB1
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
3
UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX.
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
=100pF, I
OH
/I
OL
=-1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10% , T
A
= -20
℃
to 80
℃
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT621024(E)
-35
MIN.
MAX.
35
-
-
35
-
35
-
25
10
-
5
-
-
25
-
25
5
-
UT621024(E)
-55
MIN.
MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
30
-
30
5
-
UT621024(E)
-70
MIN. MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
35
-
35
5
-
UNIT
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
*
t
WHZ
*
UT621024(E)
-35
MIN.
MAX.
35
-
30
-
30
-
0
-
25
-
0
-
20
-
0
-
5
-
-
15
UT621024(E) UT621024(E) UNIT
-55
-70
MIN.
MAX.
MIN. MAX.
55
-
70
-
ns
50
-
60
-
ns
50
-
60
-
ns
0
-
0
-
ns
40
-
45
-
ns
0
-
0
-
ns
25
-
30
-
ns
0
-
0
-
ns
5
-
5
-
ns
-
20
-
25
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
4
UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
Address
t
AA
t
OH
Dout
Previous data valid
Data Valid
t
OH
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
Address
t
AA
CE
t
ACE
CE2
OE
t
OE
t
CLZ
t
OLZ
Dout
High-Z
Data Valid
t
CHZ
t
OHZ
t
OH
High-Z
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured± 500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
5
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