UTRON
Rev 1.7
UT61L1024
128K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
REVISION
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev.1.4
Rev. 1.5
DESCRIPTION
Original.
Add TSOP-I Package
Modify the format of power consumption
1. V
OH
: 2.4 -> 2.2
2. Input Rise & Fall times : 5->3ns
3. The symbols CE1# ,OE# & WE# are revised as
CE1 , OE &
WE
Add SOP Package.
1. Revised TSOP-
Ⅰ
/STSOP pin configuration typing error
：
Pin 5=
WE
、
pin 6=CE2
2. Revised package outline dimension
1. Revised Vcc:
Rev. 1.5 : Vcc=3.1V~3.6V
Rev. 1.6 : Vcc=3.0V~3.6V
2. Add data retention characteristics and waveforms
3. Revised function block diagram
1. Add order information for lead free product
2. Revised timing read/write waveform
3. Add *V
IL
=-3.0V for pulse width less than 10ns into DC table
Released Date
Apr. 05 2000
Aug. 29.2000
Sep. 01.2000
Jun. 18,2001
Jul. 6,2001
Apr 16,2002
Rev. 1.6
May 8,2002
Rev. 1.7
May 22,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80034
UTRON
Rev 1.7
UT61L1024
128K X 8 BIT HIGH SPEED CMOS SRAM
GENERAL DESCRIPTION
The UT61L1024 is a 1,048,576-bit high-speed
CMOS static random access memory organized
as 131,072 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT61L1024 is designed for high-speed
system applications. It is particularly suited for use
in high-density high-speed system applications.
The UT61L1024 operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.
FEATURES
Fast access time : 12/15ns (max.)
Low power operating : 60mA (typ.)
Single 3.0V~3.6V power supply
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 300 mil skinny PDIP
32-pin 300 mil SOJ
32-pin 450mil SOP
32-pin 8mm x 20mm TSOP-1
32-pin 8mm x 13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
2048 X 512
MEMORY
ARRAY
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
1
2
3
4
32
31
30
29
Vcc
A15
CE2
WE
A0-A16
DECODER
Vcc
Vss
UT61L1024
5
6
7
8
9
10
11
12
13
14
15
16
28
27
26
25
24
23
22
21
20
19
18
17
A13
A8
A9
A11
OE
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
A4
A3
A2
A1
A0
I/O1
I/O2
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
CE
CE2
OE
WE
I/O3
CONTROL
CIRCUIT
Vss
PDIP / SOJ/SOP
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
UT61L1024
25
24
23
22
21
20
19
18
17
TSOP-I/STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80034
1
UTRON
Rev 1.7
UT61L1024
128K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to Vss
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
0 to 70
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
Note:
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High -Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,I
SB1
I
SB
,I
SB1
I
CC
I
CC
I
CC
H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V
∼
3.6V, T
A
= 0
℃
to 70
℃
)
PARAMETER
Power Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
Standby Power
Supply Current
V
OH
V
OL
I
CC
I
SB
I
SB1
SYMBOL
Vcc
V
IH
*
V
IL
I
LI
I
LO
TEST CONDITION
MIN.
3.0
2.0
- 0.5
-1
-1
2.2
-
-
-
-
-
MAX.
3.6
V
CC
+0.5
0.6
1
1
-
0.4
100
90
20
3
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC
CE = V
IH
or CE2 = V
IL
or
OE
= V
IH
or
WE
= V
IL
I
OH
= - 4mA
I
OL
= 8mA
Cycle time=Min, I
I/O
= 0mA
. CE = V
IL
, CE2 = V
IH
CE = V
IH
or CE2 = V
IL
CE
≧
V
CC
-0.2V ;or CE2
≦
0.2V
- 12
- 15
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 8ns.
2. Undershoot : Vss-3.0v for pulse width less than 8ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80034
2
UTRON
Rev 1.7
UT61L1024
128K X 8 BIT HIGH SPEED CMOS SRAM
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX.
8
10
UNIT
pF
pF
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
3ns
1.5V
C
L
=30pF, I
OH
/I
OL
=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V
∼
3.6V , T
A
= 0
℃
to 70
℃
)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
t
WC
t
AW
t
CW1
, t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
UT61L1024-12 UT61L1024-15
MIN.
MAX. MIN.
MAX.
12
-
15
-
10
-
12
-
10
-
12
-
0
-
0
-
9
-
10
-
0
-
0
-
7
-
8
-
0
-
0
-
3
-
4
-
-
7
-
8
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t
RC
t
AA
t
ACE1
, t
ACE1
t
OE
t
CLZ1*
, t
CLZ2*
t
OLZ*
t
CHZ1*
, t
CHZ2*
t
OHZ*
t
OH
UT61L1024-12 UT61L1024-15
MIN.
MAX. MIN.
MAX.
12
-
15
-
-
12
-
15
-
12
-
15
-
6
-
7
3
-
4
-
0
-
0
-
-
6
-
7
-
6
-
7
3
-
3
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80034
3
UTRON
Rev 1.7
UT61L1024
128K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
Address
t
AA
t
OH
Dout
Previous data valid
Data Valid
t
OH
READ CYCLE 2
(
CE
and
CE2
and
OE
Controlled)
(1,3,4,5)
t
RC
Address
t
AA
CE
t
ACE
CE2
OE
t
OE
t
CLZ
t
OLZ
Dout
High-Z
Data Valid
t
CHZ
t
OHZ
t
OH
High-Z
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
,
CE2=high
.
3.Address must be valid prior to or coincident with CE =low
,
CE2=high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ
.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80034
4
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