ESMT
SDRAM
M12L2561616A (2A)
Automotive Grade
4M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
(self refresh is not supported for VA grade)
Refresh
- 64ms refresh period (8K cycle) for V grade
- 16ms refresh period (8K cycle) for VA grade
GENERAL DESCRIPTION
The M12L2561616A is 268,435,456 bits synchronous high
data rate Dynamic RAM organized as 4 x 4,194,304 words
by 16 bits. Synchronous design allows precise cycle
control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating
frequencies,
programmable
burst
length
and
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID
Max Freq.
Package
Comments
Automotive range (V): -40℃ to +85℃
M12L2561616A-5TVG2A
M12L2561616A-6TVG2A
M12L2561616A-7TVG2A
M12L2561616A-5BVG2A
M12L2561616A-6BVG2A
M12L2561616A-7BVG2A
200MHz
166MHz
143MHz
200MHz
166MHz
143MHz
54 pin TSOP(II)
54 pin TSOP(II)
54 pin TSOP(II)
54 ball BGA
54 ball BGA
54 ball BGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Automotive range (VA): -40℃ to +105℃
M12L2561616A-5TVAG2A
M12L2561616A-6TVAG2A
M12L2561616A-7TVAG2A
M12L2561616A-5BVAG2A
M12L2561616A-6BVAG2A
M12L2561616A-7BVAG2A
200MHz
166MHz
143MHz
200MHz
166MHz
143MHz
54 pin TSOP(II)
54 pin TSOP(II)
54 pin TSOP(II)
54 ball BGA
54 ball BGA
54 ball BGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
1/46
ESMT
BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
M12L2561616A (2A)
Automotive Grade
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank A
Sense Amplifier
Command Decoder
Control Logic
L(U)DQM
CS
RAS
CAS
WE
Column
Address
Buffer
&
Counter
Column Decoder
Input & Output
Buffer
Latch Circuit
Data Control Circuit
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
2/46
ESMT
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
M12L2561616A (2A)
Automotive Grade
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
A12
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A12
BA1, BA0
RAS
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA12, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
CAS
WE
L(U)DQM
DQ0 ~ DQ15
V
DD
/ V
SS
V
DDQ
/ V
SSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
3/46
ESMT
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
A
(V grade)
T
A
(VA grade)
T
STG
P
D
I
OS
Value
M12L2561616A (2A)
Automotive Grade
Unit
V
V
°
C
°
C
°
C
W
mA
-1.0 ~ 4.6
-1.0 ~ 4.6
-40 ~ +85
-40 ~ +105
-55 ~ +150
1
50
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
μ
A
μ
A
Note
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
, all other pins are not under test = 0V.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°
C , f = 1MHz)
Parameter
Input capacitance (A0 ~ A12, BA0 ~ BA1)
Input capacitance (CLK)
Input capacitance
(CKE, CS , RAS , CAS ,
WE
& L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
Symbol
C
IN1
C
CLK
C
IN2
C
OUT
Min
1.5
2
1.5
2
Max
3
3
4.5
4.5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
4/46
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
M12L2561616A (2A)
Automotive Grade
Version
-5
-6
70
1
1
15
5
6
6
-7
60
Unit Note
I
CC1
Burst Length = 2, t
RC
= t
RC
(min), I
OL
= 0 mA
CKE = V
IL
(max), t
CC
= 10ns
CKE & CLK=V
IL
(max), t
CC
=
∞
CKE=V
IH
(min), CS = V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 2CLK
CKE=V
IH
(min), CLK=V
IL
(max), t
CC
=
∞
input signals are stable
CKE=V
IL
(max), t
CC
=10ns
CKE & CLK=V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
80
mA
mA
mA
mA
mA
mA
mA
1,2
Precharge Standby
I
CC2P
Current in power-down
mode
I
CC2PS
Precharge Standby
Current in non
power-down mode
I
CC2N
I
CC2NS
Active Standby
I
CC3P
Current in power-down
I
CC3PS
mode
Active Standby
Current in non
power-down mode
(One Bank Active)
I
CC3N
Input signals are changed one time during 2 CLKs
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE=V
IH
(min), CLK=V
IL
(max), t
CC
=
∞
input signals are stable
I
OL
= 0 mA, Page Burst, 4 Banks activated,
t
CCD
= 2 CLKs
t
RFC
≥
t
RFC
(min)
CKE=0.2V
90
120
28
mA
I
CC3NS
I
CC4
I
CC5
I
CC6
20
80
110
3
70
100
mA
mA
mA
mA
1,2
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note: 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKs.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
5/46
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