NT512T72U89A0BD / NT512T72U89A0BN / NT512T72U89A0BE
NT1GT72U8PA0BD / NT1GT72U8PA0BN / NT1GT72U8PA0BE
NT2GT72U4NA0BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 128Mx72
Preliminary
240pin DDR2 SDRAM Fully Buffered DIMM
Based on 64Mx8 & 128Mx4 DDR2 SDRAM
Features
• 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8
DDR2 SDRAM.
• 1GB 128Mx72 DDR2 Fully Buffered DIMM based on 64Mx8
DDR2 SDRAM.
• 2GB 128Mx72 DDR2 Fully Buffered DIMM based on 128Mx4
DDR2 SDRAM.
• JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line
Memory Module.
• Performance:
PC2-4200
Speed Sort
DIMM
Latency
*
f
CK
t
CK
f
DQ
Clock
Frequency
Clock
Cycle
DQ Burst
Frequency
-4B
4
266
3.75
533
PC2-5300
-3C
5
333
3
667
MHz
ns
MHz
Unit
• Intended for 266MHz and 333MHz applications.
• Inputs and outputs are SSTL-18 compatible.
• V
DD
= 1.8Volt ± 0.1, V
DDQ
= 1.8Volt ± 0.1.
• Host Interface and AMB component industry standard
compliant.
• Support SMBus protocol interface for access to the AMB
configuration registers.
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• MBIST & IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Serial Presence Detect (SPD)
• Gold contacts
• RoHs Compliant products.
• SDRAMs in 60-ball FBGA Package
Description
NT512T72U89A0BD, NT512T72U89A0BN, NT512T72U89A0BE, NT1GT72U8PA0BD, NT1GT72U8PA0BN, NT1GT72U8PA0BE, and
NT2GT72U4NA0BN are Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one bank 64Mx72 & 128Mx72 high-speed memory array. The module uses nine 64Mx8 (512MB), eighteen 64Mx8 (1GB),
and thirty-six 128Mx4 (2GB) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad
industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA
DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 333 MHz clock speeds and achieves high-speed data transfer rates of up to
667 MHz. Prior to any access operation, the device
latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 0.4
10/06/2005
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A0BD / NT512T72U89A0BN / NT512T72U89A0BE
NT1GT72U8PA0BD / NT1GT72U8PA0BN / NT1GT72U8PA0BE
NT2GT72U4NA0BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 128Mx72
Preliminary
Ordering Information
Part Number
NT512T72U89A0BD-4B
NT512T72U89A0BN-4B
NT512T72U89A0BE-4B
NT1GT72U8PA0BD-4B
NT1GT72U8PA0BN-4B
NT1GT72U8PA0BE-4B
NT2GT72U4NA0BN-4B
NT512T72U89A0BD-3C
NT512T72U89A0BN-3C
NT512T72U89A0BE-3C
NT1GT72U8PA0BD-3C
NT1GT72U8PA0BN-3C
NT1GT72U8PA0BE-3C
NT2GT72U4NA0BN-3C
AMB
IDT
INTEL
NEC
IDT
INTEL
NEC
INTEL
IDT
INTEL
NEC
IDT
INTEL
NEC
INTEL
333MHz
(3ns @ CL = 5)
64Mx72
266MHz
(2.75ns @ CL = 4)
64Mx72
Speed
Organization
Leads
Power
DDR2-533
PC2-4200
128Mx72
Gold
1.8V
DDR2-667
PC2-5300
128Mx72
REV 0.4
10/06/2005
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A0BD / NT512T72U89A0BN / NT512T72U89A0BE
NT1GT72U8PA0BD / NT1GT72U8PA0BN / NT1GT72U8PA0BE
NT2GT72U4NA0BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 128Mx72
Preliminary
DIMM Connector Pin Description
Pin Name
SCK
PN0-PN13
-
PS0-PS9
-
SN0-SN13
-
SS0-SS9
-
SCL
SDA
SA0-SA2
VID0-VID1
Pin Description
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address Inputs, also used to select the DIMM number in the AMB
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID0 is V
DD
value: OPEN=1.8V, GND=1.5V; VID1 is V
CC
value: OPEN=1.5V, GND=1.2V
AMB reset signal
RFU
V
CC
V
DD
V
TT
V
DDSPD
V
SS
Reserved for Future Use
AMB Core Power and AMB Channel Interface Power (1.5V)
DRAM Power and AMB DRAM I/O Power (1.8V)
DRAM Address/Command/Clock Termination Power (V
DD
/2)
SPD Power
Ground
It provides an external connection on R/Cs A-D for testing the margin of V
ref
which is
produced by a voltage divider on the module. It is not intended to be used in normal
system operation and must not be connected (DNU) in a system. This test pin may have
other features on future card designs and if it does, will be included in this specification at
that time
2
Note
1
1
DNU/M_TEST
1
Note:
1.
2.
System Clock Signals SCK and SCK switch at one half the DRAM CK/
frequency
Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
REV 0.4
10/06/2005
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A0BD / NT512T72U89A0BN / NT512T72U89A0BE
NT1GT72U8PA0BD / NT1GT72U8PA0BN / NT1GT72U8PA0BE
NT2GT72U4NA0BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 128Mx72
Preliminary
DDR2 240-pin FBDIMM Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
V
SS
PN13
V
SS
PN5
V
SS
PN4
V
SS
PN3
V
SS
PN2
69
70
71
72
73
74
75
76
77
78
79
80
81
V
SS
V
SS
PS3
V
SS
PS2
V
SS
PS1
V
SS
PN1
V
SS
RFU**
RFU**
V
SS
PN0
Front Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID1
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
V
SS
KEY
V
SS
PS0
V
SS
PN11
V
SS
PN10
V
SS
PN9
V
SS
PN8
V
SS
PN7
V
SS
PN6
Front Side
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
PN12
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
RFU**
RFU**
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
SA2
SDA
SCL
V
SS
PS8
V
SS
PS7
V
SS
PS6
V
SS
PS5
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
PS9
Front Side
PS4
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
SN13
V
SS
SN5
V
SS
SN4
V
SS
SN3
V
SS
SN2
189
190
191
192
193
194
195
196
197
198
199
200
201
V
SS
V
SS
SS3
V
SS
SS2
V
SS
SS1
V
SS
SN1
Back Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID0
DNU/M_TEST
V
SS
RFU**
RFU**
V
SS
SN0
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
V
SS
KEY
V
SS
SS0
V
SS
SN11
V
SS
SN10
V
SS
SN9
V
SS
SN8
V
SS
SN7
V
SS
SN6
Back Side
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
SN12
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
V
DDSPD
SA0
SA1
V
SS
RFU**
RFU**
V
SS
SCK
V
SS
SS8
V
SS
SS7
V
SS
SS6
V
SS
SS5
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
SS9
Back Side
SS4
Note:
RFU = Reserved Future Use
* These pin positions are reserved for forwarded clocks to be used in future module implementation
** These pin positions are reserved for future architecture flexibility
The following signals are CRC bits and thus appear out of the normal sequence: PN12/
, SN12/
PS9/
, SS9/
, PN13/
, SN13/
,
REV 0.4
10/06/2005
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A0BD / NT512T72U89A0BN / NT512T72U89A0BE
NT1GT72U8PA0BD / NT1GT72U8PA0BN / NT1GT72U8PA0BE
NT2GT72U4NA0BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 128Mx72
Preliminary
Input/Output Functional Description
Symbol
SCK,
PN0-PN13,
PS0-PS9,
SN0-SN13,
SS0-SS9,
SA0-SA2
SDA
SCL
-
-
-
-
Type
Input
Output
Input
Input
Output
Input
I/O
Input
Polarity
Channel Signal
Differential System Clock Input
Differential Primary Northbound Data
Differential Primary Southbound Data
Differential Secondary Northbound Data
Differential Secondary Southbound Data
SMB Bus Signal
-
-
-
Active
Low
0.9V
-
1.8V
1.5V
3.3V
Positive
Edge
SPD Address/used to select the DIMM number in the AMB
SPD Data. A resistor must connected from the SDA
system planar to act as a pull-up.
SPD Clock
Miscellaneous Signals
Input
TEST
VID0-VID1
Analog
Input
Supply
Supply
Supply
(SSTL)
(SSTL)
CKE0, CKE1
(SSTL)
AMB Reset Signal
DRAM V
REF
Margin Test. Do not connect on the system planar.
Voltage ID. Both pins shall be NC in case of V
DD
=1.8V & V
CC
=1.5V
Power / Ground
V
DD
V
CC
V
DDSPD
CK0
DDR2 DRAM Power
AMB Core Power
SPD Power
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on
the rising edge of their associated clocks.
bus line to VDDSPD on the
Function
Negative The negative line of the differential pair of system clock inputs which drives the input to
Edge
the on-DIMM PLL.
Active
High
Active
Low
Active
Low
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock,
operation to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
Isolated power supply for the DDR2 SDRAM output buffers to provide improved noise
immunity
Active
High
-
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of
the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM
configurations.
Power and ground for the DDR SDRAM input buffers and core logic
,
(SSTL)
,
V
REF
,
(SSTL)
Supply
Supply
Input
(SSTL)
,
,
define the
V
DDQ
ODT0, ODT1
BA0, BA1
A0 - A9
A10/AP
A11, A12
(SSTL)
-
DQ0 – DQ63
CB0 – CB7
V
DD,
V
SS
(SSTL)
Supply
Active
High
REV 0.4
10/06/2005
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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