ESMT
Mobile SDRAM
M52D128324A (2E)
1M x 32Bit x 4Banks
Mobile Synchronous DRAM
FEATURES
1.8V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-
CAS Latency (2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
Special Function Support
-
PASR (Partial Array Self Refresh )
-
TCSR (Temperature Compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M52D128324A is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 1,048,576 words
by 32 bits, fabricated with high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
Product ID
M52D128324A -5BG2E
M52D128324A -6BG2E
M52D128324A -7BG2E
Max
Freq.
Package
Comments
Pb-free
Pb-free
Pb-free
200MHz 90 Ball BGA
166MHz 90 Ball BGA
143MHz 90 Ball BGA
BALL CONFIGURATION (TOP VIEW)
(BGA90, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)
1
A
B
2
3
4
5
6
7
8
9
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
C VSSQ DQ27 DQ25
D VSSQ DQ29 DQ30
E VDDQ DQ31
F
G
H
J
VSS DQM3
A4
A7
CLK
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
WE
A1
A11
RAS
K DQM1
DQM0
L VDDQ DQ8
VDD
DQ6
DQ1
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
M VSSQ DQ10 DQ9
N VSSQ DQ12 DQ14
P
R
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2012
Revision
:
1.0
1/31
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
M52D128324A (2E)
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Address
Mode
Register
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM0~3
Column Decoder
DQ
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A11
BA0, BA1
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power /
Ground
No Connection
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
DQM0~3
DQ0~31
VDD/VSS
VDDQ/VSSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2012
Revision
:
1.0
2/31
ESMT
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Operation ambient temperature
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
T
A
T
STG
P
D
I
OS
Value
-1.0 ~ 2.6
-1.0 ~ 2.6
0 ~ +70
M52D128324A (2E)
Unit
V
V
℃
℃
W
mA
-55 ~ + 150
0.7
50
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
,V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
Min
1.7
0.8 x V
DDQ
-0.3
V
DDQ
- 0.2
-
-2
Typ
1.8
1.8
0
-
-
-
Max
1.95
V
DDQ
+0.3
0.3
-
0.2
2
Unit
V
V
V
V
V
uA
Note
1
2
3
I
OH
=-0.1mA
I
OL
= 0.1mA
4
Note: 1. Under all conditions. V
DDQ
must be less than or equal to V
DD
.
2. V
IH
(max) = 2.2V AC. The overshoot voltage duration is
≤
3ns.
3. V
IL
(min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
CAPACITANCE
(V
DD
= 1.8V, T
A
= 25℃, f = 1MHz)
Pin
CLOCK
RAS , CAS ,
WE
, CS , CKE, DQM0~3
ADDRESS
DQ0 ~DQ31
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2012
Revision
:
1.0
3/31
ESMT
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Test Condition
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA, Page Burst
All Bank Activated, t
CCD
= t
CCD
(min)
t
RFC
≥
t
RFC
(min)
TCSR range
Full array
Self Refresh Current
I
CC6
CKE
≤
0.2V
1/2 array
1/4 array
1/8 array
Deep Power Down
Current
I
CC7
CKE
≤
0.2V
M52D128324A (2E)
Version
-5
55
-6
50
900
900
10
10
3
1
20
-7
45
Unit Note
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
mA
uA
uA
mA
mA
mA
1
I
CC3P
Active Standby Current
in power-down mode
I
CC3PS
Active Standby Current I
CC3N
in non power-down
mode
(One Bank Active)
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
I
CC4
I
CC5
mA
7
100
70
45
950
900
850
800
10
90
65
80
60
85
1000
950
900
850
mA
mA
mA
1
2
°C
uA
uA
Note: 1. Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2. Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2012
Revision
:
1.0
4/31
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
= 1.7V~1.95V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
1.8V
M52D128324A (2E)
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
Vtt =0.5x VDDQ
13.9K
50
Unit
V
V
ns
V
Output
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
Output
Z0=50
20 pF
10.6K
20 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto refresh
Symbol
-5
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
MRD
(min)
t
REF
(max)
CAS Latency=3
CAS Latency=2
10
15
15
40
55
55
Version
-6
12
18
18
42
100
60
60
1
2
1
1
2
64
2
1
-7
14
21
21
42
63
63
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
CLK
ms
ea
1
1
1
1
-
1
1,6
2
2
2
3
-
5
4
Unit
Note
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or
Refresh command
Refresh period (4,096 rows)
Number of valid output data
Note:
1.
2.
3.
4.
5.
6.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6
μ
s.)
A new command may be given t
RFC
after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Aug. 2012
Revision
:
1.0
5/31
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