NT512D64S8HBAFM / NT512D64S8HB0FN
NT256D64SH8B0GM / NT256D64SH8B0GN / NT256D64SH8BAGM
NT128D64SH4B0GM / NT128D64SH4B0GN / NT128D64SH4BBGM
512MB, 256MB and 128MB
PC2700 and PC2100
Unbuffered DDR SO-DIMM
200 pin Unbuffered DDR SO-DIMM
Based on DDR333/266 256M bit B Die device
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• Unbuffered DDR SO-DIMM based on 256M bit die B device,
organized as either 32Mbx8 or 16Mbx16
• Performance:
PC2700 PC2100
Speed Sort
f
CK
t
CK
Clock Frequency
Clock Cycle
6K
2.5
166
6
333
75B
2.5
133
7.5
266
MHz
ns
MHz
Unit
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
Latency: 2, 2.5, 3
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts
• SDRAMs are packaged in CSP or TSOP packages
• “Green” packaging – lead free
f
DQ
DQ Burst Frequency
• Intended for 133 and 166 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= V
DDQ
= 2.5V ± 0.2V
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions
Description
NT512D64S8HBAFM, NT512D64S8HB0FN, NT256D54SH8BAGM, NT256D54SH8B0GM, NT256D54SH8B0GN, NT128D64SH4BBGM ,
NT128D64SH4B0GM and NT128D64SH4B0GN are unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual
In-Line Memory Modules (SO-DIMM). NT512D64S8HBAFM and NT512D64S8HB0FN are 512MB modules, organized as dual ranks using
sixteen 32Mx8 CSP devices with NT512D64S8HB0FN being lead free. NT256D54SH8BAGM, NT256D54SH8B0GM and
NT256D54SH8B0GN are 256MB modules, organized as dual ranks using eight 16Mx16 TSOP devices with NT256D54SH8B0GN being
lead free. NT128D64SH4BBGM, NT128D64SH4B0GM and NT128D64SH4B0GN are 128MB modules, organized as single rank using
four 16Mx16 TSOP devices.
Depending on the speed grade, these SO-DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves
type must be programmed into the SO-DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The SO-DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can
be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC and the remaining
are available for use by the customer.
REV 2.0
Mar 4, 2004
1
NANYA reserves the right to change products and specifications without notice.
Preliminary
SAC
high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device
SAC
DIMM
Latency
SAC
latency and burst type/ length/operation
© NANYA TECHNOLOGY CORPORATION
NT512D64S8HBAFM / NT512D64S8HB0FN
NT256D64SH8B0GM / NT256D64SH8B0GN / NT256D64SH8BAGM
NT128D64SH4B0GM / NT128D64SH4B0GN / NT128D64SH4BBGM
Unbuffered DDR SO-DIMM
Ordering Information
Part Number
NT512D64S8HBAFM-6K
NT512D64S8HB0FN-6K
(lead free)
Organization
Speed
Power
Leads
64Mx64
NT256D64SH8BAGM-6K
32Mx64
NT256D64SH8B0GN-6K
(lead free)
PC2700 166MHz (6ns @ CL = 2.5)
DDR333
2.5-3-3 133MHz (7.5ns @ CL = 2)
NT128D64SH4BBGM-6K
16Mx64
NT128D64SH4B0GN-6K
(lead free)
NT512D64S8HBAFM-75B
64Mx64
NT512D64S8HB0FN-75B
(lead free)
2.5V
Gold
NT256D64SH8BAGM-75B
NT256D64SH8B0GM-75B
NT256D64SH8B0GN-75B
(lead free)
32Mx64
DDR266B
PC2100 133MHz (7.5ns @ CL = 2.5)
2.5-3-3 100MHz (10ns @ CL = 2)
NT128D64SH4B0GM-75B
NT128D64SH4BBGM-75B
NT128D64SH4B0GN-75B
(lead free)
16Mx64
For the closest sales office or information, please visit:
www.nanya.com
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
REV 2.0
Mar 4, 2004
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
Preliminary
NT512D64S8HBAFM / NT512D64S8HB0FN
NT256D64SH8B0GM / NT256D64SH8B0GN / NT256D64SH8BAGM
NT128D64SH4B0GM / NT128D64SH4B0GN / NT128D64SH4BBGM
Unbuffered DDR SO-DIMM
Pin Description
CK0, CK1, CK2,
A0-A9, A11, A12
A10/AP
BA0, BA1
V
REF
V
DDID
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
Pin Back
2
4
6
8
V
REF
V
SS
DQ4
DQ5
Pin Front
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
NC
NC
V
SS
DQS8
NC
V
DD
NC
DU
V
SS
CK2
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Back
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
NC
NC
V
SS
NC
NC
V
DD
NC
DU
V
SS
V
SS
V
DD
V
DD
CKE0
DU
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Front
A9
V
SS
A7
A5
A3
A1
V
DD
A10/AP
BA0
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
Pin Front
151 DQ42
153 DQ43
155 V
DD
157 V
DD
159 V
SS
161 V
SS
163 DQ48
165 DQ49
167 V
DD
169 DQS6
171 DQ50
173 V
SS
175 DQ51
177 DQ56
179 V
DD
181 DQ57
183 DQS7
185 V
SS
187 DQ58
189 DQ59
191 V
DD
193 SDA
195 SCL
197 V
DDSPD
199 V
DDID
Pin Back
152 DQ46
154 DQ47
156 V
DD
10 V
DD
12 DM0
14 DQ6
16 V
SS
18 DQ7
20 DQ12
22 V
DD
24 DQ13
26 DM1
28 V
SS
30 DQ14
32 DQ15
34 V
DD
36 V
DD
38 V
SS
40 V
SS
42 DQ20
44 DQ21
46 V
DD
48 DM2
50 DQ22
160 CK1
162 V
SS
164 DQ52
166 DQ53
168 V
DD
170 DM6
172 DQ54
174 V
SS
176 DQ55
178 DQ60
180 V
DD
182 DQ61
184 DM7
186 V
SS
188 DQ62
190 DQ63
192 V
DD
194 SA0
196 SA1
198 SA2
200 DU
DU
DU
V
SS
DQ32
DQ33
V
DD
DQS4
DQ34
V
SS
DQ35
DQ40
V
DD
DQ41
DQS5
V
SS
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
V
SS
DQ17
V
DD
DQS2
DQ18
V
DD
CKE1
DU
A12
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 2.0
Mar 4, 2004
Preliminary
2KC
DQ16
100 A11
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
1KC
1S
SAC
SAR
0S
EW
2KC 1KC 0KC
CKE0, CKE1
,
,
Differential Clock Inputs.
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-precharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
DQ0-DQ63
DQS0-DQS7
DM0-DM7
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bidirectional data strobes
Input Data Mask
Power
Supply voltage for DQs
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply
1S 0S
EW
SAC
SAR
,
158
0KC
NT512D64S8HBAFM / NT512D64S8HB0FN
NT256D64SH8B0GM / NT256D64SH8B0GN / NT256D64SH8BAGM
NT128D64SH4B0GM / NT128D64SH4B0GN / NT128D64SH4BBGM
Unbuffered DDR SO-DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2,
(SSTL)
Type
Polarity
Cross
point
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
REV 2.0
Mar 4, 2004
Preliminary
EW SAC SAR
,
,
(SSTL)
Supply
Supply
(SSTL)
V
REF
V
DDQ
BA0, BA1
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, these lines define the row address when sampled
at the rising clock edge.
During a Read or Write command cycle, these lines defines the column address when
sampled at the rising clock edge. In addition to the column address, AP is used to invoke
auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data. DQS8 is used for ECC modules
(CB0-CB7) and is not used on x64 modules.
Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the Serial
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
A0 - A9
A10/AP
A11 - A13
(SSTL)
-
DQ0 - DQ63
(SSTL)
-
Active
High
-
Active
High
DQS0 – DQS8
CB0 – CB7
DM0 – DM8
V
DD
, V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
(SSTL)
(SSTL)
Input
Supply
-
-
-
Supply
4
NANYA reserves the right to change products and specifications without notice.
EW SAC SAR
2KC 1KC 0KC
CKE0, CKE1
(SSTL)
,
,
1S 0S
,
(SSTL)
Active
Low
Active
Low
When sampled at the positive rising edge of the clock,
be executed by the SDRAM.
,
,
define the operation to
© NANYA TECHNOLOGY CORPORATION
NT512D64S8HBAFM / NT512D64S8HB0FN
NT256D64SH8B0GM / NT256D64SH8B0GN / NT256D64SH8BAGM
NT128D64SH4B0GM / NT128D64SH4B0GN / NT128D64SH4BBGM
Unbuffered DDR SO-DIMM
Functional Block Diagram
2 Ranks, 16 devices, 32Mbx8 DDR SDRAMs
0S
1S
D0
D1
D2
D3
BA0-BA1 : SDRAMs D0-D15
A0-A12 : SDRAMs D0-D15
: SDRAMs D0-D15
: SDRAMs D0-D15
CKE : SDRAMs D0-D7
CKE : SDRAMs D8-D15
: SDRAMs D0-D15
SCL
WP
Serial PD
A0
SA0
DQ-to-I/O wring may be changed within a byte.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22 Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
A1
SA1
A2
SA2
SDA
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D8
D4
D9
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D10
D6
D11
D7
BA0-BA1
A0-A12
V
DDSPD
V
DD
/V
DDQ
VR
EF
V
SS
V
DDID
SPD
D0-D15
D0-D15
D0-D15
Strap: see Note 4
CKE0
CKE1
Notes :
1.
2.
3.
4.
REV 2.0
Mar 4, 2004
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
Preliminary
SC
SC
SC
SC
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
SC
SC
SC
SC
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
SC
SC
SC
SC
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
SC
D12
D13
D14
D15
SC
SC
SC
SAC
SAR
EW
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
DQS
DQS
DQS
SAC
SAR
EW
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