PPJA3432
30V N-Channel Enhancement Mode MOSFET – ESD Protected
Voltage
Features
RDS(ON) , VGS@4,5V, ID@1.6A<200mΩ
RDS(ON) , VGS@2.5V, ID@1.1A<270mΩ
RDS(ON) , VGS@1.8V, ID@0.2A<570mΩ
Advanced Trench Process Technology
Specially Designed for Switch Load, PWM Application, etc.
ESD Protected 2KV HBM
Lead free in compliance with EU RoHS 2011/65/EU directive.
Green molding compound as per IEC61249 Std.
30 V
Current
1.6A
SOT-23
Unit: inch(mm)
(Halogen Free)
Mechanical Data
Case: SOT-23 Package
Terminals : Solderable per MIL-STD-750, Method 2026
Approx. Weight: 0.0003 ounces, 0.0084 grams
Marking: A32
Maximum Ratings and Thermal Characteristics
(T
A
=25 C unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Power Dissipation
(Note 4)
o
SYMBOL
V
DS
V
GS
I
D
I
DM
T
a
=25
o
C
Derate above 25
o
C
P
D
T
J
,T
STG
R
θJA
LIMIT
UNITS
V
V
A
A
W
mW/
o
C
o
30
+8
1.6
6.4
1.25
10
-55~150
100
o
Operating Junction and Storage Temperature Range
Typical Thermal resistance
-
Junction to Ambient
(Note 3)
C
C/W
January 22,2015-REV.02
Page 1
PPJA3432
Electrical Characteristics
(T
A
=25 C unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
BV
DSS
V
GS(th)
R
DS(on)
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
Ciss
Coss
Crss
td
(on)
tr
td
(off)
tf
V
GS
=0V, I
D
=250uA
V
DS
=V
GS
, I
D
=250uA
V
GS
=4.5V, I
D
=1.6A
Drain-Source On-State Resistance
V
GS
=2.5V, I
D
=1.1A
V
GS
=1.8V, I
D
=0.2A
Zero Gate Voltage Drain Current
Gate-Source Leakage Current
Dynamic
(Note 5)
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Drain-Source Diode
Maximum Continuous Drain-Source
Diode Forward Current
Diode Forward Voltage
I
S
V
SD
---
I
S
=1.0A, V
GS
=0V
-
-
-
0.81
1.0
1.2
A
V
V
DS
=15V, I
D
=1.6A,
V
GS
=4.5V
(Note 1,2)
V
DS
=15V, V
GS
=0V,
f=1.0MHZ
V
DD
=15V, I
D
=1.6A,
V
GS
=4.5V,
R
G
=6Ω
(Note 1,2)
-
-
-
-
-
-
-
-
-
-
1.5
0.3
0.3
93
19
6
6.4
33
37
32
-
-
-
-
-
-
-
-
-
-
ns
pF
nC
V
DS
=30V, V
GS
=0V
V
GS
=+8V, V
DS
=0V
30
0.5
-
-
-
-
-
-
0.78
145
185
330
0.01
1.4
-
1.3
200
270
570
1
+10
uA
uA
mΩ
V
V
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNITS
o
NOTES :
1. Pulse width<300us, Duty cycle<2%
2. Essentially independent of operating temperature typical characteristics.
3. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is
defined as the solder mounting surface of the drain pins mounted on a 1 inch FR-4 with 2oz. square pad of copper.
4. The maximum current rating is package limited.
5. Guaranteed by design, not subject to production testing.
January 22,2015-REV.02
Page 2
PPJA3432
TYPICAL CHARACTERISTIC CURVES
Fig.1 On-Region Characteristics
Fig.2 Transfer Characteristics
Fig.3 On-Resistance vs. Drain Current
Fig.4 On-Resistance vs. Junction temperature
Fig.5 On-Resistance Variation with VGS.
Fig.6 Body Diode Characteristics
January 22,2015-REV.02
Page 3
PPJA3432
TYPICAL CHARACTERISTIC CURVES
Fig.7 Gate-Charge Characteristics
Fig.8 Threshold Voltage Variation with Temperature.
Fig.9 Capacitance vs. Drain-Source Voltage.
January 22,2015-REV.02
Page 4
PPJA3432
PART NO PACKING CODE VERSION
PART NO PACKING CODE
Package Type
SOT-23
SOT-23
Packing type
3K pcs / 7” reel
12K pcs / 13” reel
Marking
A32
A32
Version
Halogen free
Halogen free
PJA3432_R1_00001
PJA3432_R2_00001
MOUNTING PAD LAYOUT
0.035 MIN.
(0.90) MIN.
0.031 MIN.
(0.80) MIN.
0.043
(1.10)
0.037
(0.95)
0.043
(1.10)
0.106
(2.70)
January 22,2015-REV.02
0.078
(2.00)
Page 5
FPGA/CPLD
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