AME
AME8853
n
General Description
The AME8853 family of positive, CMOS linear regula-
tors provide low dropout voltage(220mV@300mA), low
quiescent current, and low noise CMOS LDO. These
rugged devices have both Thermal Shutdown, and Cur-
rent limit to prevent device failure under the "Worst" of
operating conditions.
High PSRR, Low Noise, 300mA
CMOS Regulator
n
Typical Application
IN
IN
EN
C
IN
1µF
OUT
AME8853
GND
OUT
C
OUT
1µF
n
Features
l
Low Dropout Voltage: 220mV@300mA
l
Guaranteed Current: 300mA
l
Quiescent Current: 60µA (typ.)
l
Over-Temperature Shutdown
l
Current Limiting protection
l
PSRR: 60dB@10KHz
l
Ultra-Low-Noise: 100µV
RMS
at 1Hz to 100KHz
l
Low Temperature Coefficient
l
Input Voltage Range : 2.5V~5.5V
l
Output Voltage Range: 0.8V~ 4.3V
l
Green Products Meet RoHS Standards
EN
Thermal
Shutdown
R1
Overcurrent
Shutdown
n
Functional Block Diagram
IN
OUT
n
Applications
l
Instrumentation
l
Portable Electronics
l
Wireless Devices
l
Cordless Phones
l
PC Peripherals
l
Battery Powered Widgets
-
AMP
+
R2
Vref
GND
Rev. C.03
1
AME
AME8853
n
Pin Configuration
SC-70-5
Top View
5
4
High PSRR, Low Noise, 300mA
CMOS Regulator
SOT-25/TSOT-25A
Top View
AME8853-AIVxxx
1. IN
2. GND
5
4
AME8853-AEVxxxx
1. IN
2. GND
AME8853
AME8853
3. EN
4. NC
5. OUT
1
3. EN
4. NC
5. OUT
1
2
3
2
3
* Die Attach:
Conductive Epoxy
* Die Attach:
Conductive Epoxy
SOT-23
Top View
3
SC-70-4 (SC-82)
Top View
AME8853-AETxxx
1. GND
2. OUT
4
3
AME8853-AIUxxx
1. EN
2. GND
3. OUT
4. IN
AME8853
AME8853
3. IN
* Die Attach:
Non-Conductive Epoxy
1
2
1
2
* Die Attach:
Conductive Epoxy
2
Rev. C.03
AME
AME8853
n
Pin Description
SC-70-5
High PSRR, Low Noise, 300mA
CMOS Regulator
Pin Number Pin Name
1
IN
Pin Description
Input voltage pin; should be decoupled with 1µF or greater capacitor.
2
GND
Ground connection pin.
Enable pin, Active “high". When pulled “low”, the PMOS pass transistor turns off,
current consuming less than 1µA. When EN pin float outside, it’ weakly pulled
s
high form internal MOS.
No connection.
LDO voltage regulator output pin; should be decoupled with a 1.0µF or greater
value low ESR ceramic capacitor.
3
EN
4
NC
5
OUT
SOT-25/TSOT-25A
Pin Number Pin Name
1
IN
Pin Description
Input voltage pin; should be decoupled with 1µF or greater capacitor.
2
GND
Ground connection pin.
Enable pin, Active “high". When pulled “low”, the PMOS pass transistor turns off,
current consuming less than 1µA. When EN pin float outside, it’s weakly pulled
high.
No connection.
LDO voltage regulator output pin; should be decoupled with a 1.0µF or greater
value low ESR ceramic capacitor.
3
EN
4
NC
5
OUT
Rev. C.03
3
AME
AME8853
n
Pin Description (Contd.)
SOT-23
High PSRR, Low Noise, 300mA
CMOS Regulator
Pin Number Pin Name
1
GND
Ground connection pin.
Pin Description
2
OUT
LDO voltage regulator output pin; should be decoupled with a 1.0µF or greater
value low ESR ceramic capacitor.
3
IN
Input voltage pin; should be decoupled with 1µF or greater capacitor.
SC-70-4(SC-82)
Pin Number Pin Name
1
EN
Pin Description
Enable pin, Active “high". When pulled “low”, the PMOS pass transistor turns off,
current consuming less than 1µA. When EN pin float outside, it’s weakly pulled
high.
Ground connection pin.
LDO voltage regulator output pin; should be decoupled with a 1.0µF or greater
value low ESR ceramic capacitor.
Input voltage pin; should be decoupled with 1µF or greater capacitor.
2
GND
3
OUT
4
IN
4
Rev. C.03
AME
AME8853
n
Ordering Information
AME8853 - x x x xxx x
High PSRR, Low Noise, 300mA
CMOS Regulator
Special Feature
Output Voltage
Number of Pins
Package Type
Pin Configuration
Pin Configuration
Package
Type
E: SOT-2X
I: SC-70 (SC-82)
Number of
Pins
T: 3
U: 4
V: 5
Output Voltage
Special Feature
A
(SC-70-5)
1. IN
2. GND
3. EN
4. NC
5. OUT
1. IN
2. GND
3. EN
4. NC
5. OUT
1. EN
2. GND
3. OUT
4. IN
1. GND
2. OUT
3. IN
A
(SOT-25)
(TSOT-25A)
A
(SC-70-4/
SC-82)
A
(SOT-23)
080: 0.8V
090: 0.9V
100: 1.0V
110: 1.1V
120: 1.2V
130: 1.3V
140: 1.4V
150: 1.5V
: :
180: 1.8V
: :
250: 2.5V
: :
280: 2.8V
: :
: :
420: 4.2V
430: 4.3V
N/A: SOT-2X
K: 0.9mm max height
(for TSOT-2XA Only)
Rev. C.03
5
FPGA/CPLD
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