NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG / NT5TU32M16CF
512Mb DDR2 SDRAM
Feature
CAS Latency Frequency
DDR2-533
Speed Sorts
(CL-tRCD-tRP)
Parameter
Clock
tRCD
tRP
tRC
tRAS
-37B/-37BI
4-4-4
DDR2-667
3C/-3CI
5-5-5
DDR2-800
-25D/-25DI
6-6-6
-
25C
/-
25CI(CL)
DDR2-1066
-BE
7-7-7
-BD
Units
5-5-5
6-6-6
min
125
15
15
60
max
266
-
-
-
70K
min
125
15
15
60
max
333
-
-
-
70K
min
125
15
15
60
max
400
-
-
-
70K
min
125
12.5
12.5
57.5
max
400
-
-
-
70K
min
125
13.125
13.125
58.125
max
533
-
-
-
70K
min
125
11.25
11.25
56.25
max
533
-
-
-
70K
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
5
3.75
-
-
-
45
5
3.75
3
-
-
45
5
3.75
3
2.5
-
45
5
3.75
2.5
-
-
45
5
3.75
2.5
2.5
1.875
45
5
3.75
2.5
1.875
1.875
tCK
(Avg.)
@ CL3
tCK
(Avg.)
@ CL4
tCK
(Avg.)
@ CL5
tCK
(Avg.)
@ CL6
tCK
(Avg.)
@ CL7
8
8
-
-
-
8
8
8
-
-
8
8
8
8
-
8
8
8
-
-
8
8
8
8
8
8
8
8
8
8
1.8V
±
0.1V Power Supply Voltage
4 internal memory banks
Programmable CAS Latency: 3,4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3 and 4.
Write Latency = Read Latency -1
4 and 8 programmable Sequential / Interleave Burst
Programmable Burst Length:
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Strong and Weak Strength Data-Output Driver
Auto-Refresh and Self-Refresh
Power Saving Power-Down modes
Industrial grade device support -40℃~95℃ Operating
t Temperature (-37BI/-3CI/-25DI/-25CI)
7.8 µs max. Average Periodic Refresh Interval
JEDEC Compliance
Packages:
60-Ball BGA for X4 & x8 components
84-Ball BGA for x16 component
4 bit prefetch architecture
1KB
page size for X4 & x8
2KB page size for x16
RoHS Compliance-
NT5TU128M4CE/NT5TU64M8CE/NT5TU32M16CG
4 internal memory banks
RoHS5 Compliance-
NT5TU32M16CF
Data-Strobes: Bidirectional, Differential
1
REV 1.9
Nov / 2009
CONSUMER DRAM
©
NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG / NT5TU32M16CF
512Mb DDR2 SDRAM
Description
The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM containing
536,870,912 bits. It is internally configured as a qual-bank DRAM.
The 512Mb chip is organized as either 32Mbit x 4 I/O x 4 banks, 16Mbit x 8 I/O x 4 banks or 8Mbit x 16 I/O x 4 banks
device.
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance adjustment
and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4 and x8 organized components
and a 13 bit address bus for x16 component which use for convey row, column, and bank address devices.
These devices operate with a single 1.8V
±
0.1V power supply and are available in BGA packages. An Auto-Refresh and
Self-Refresh mode is provided along with various power-saving power-down modes.
2
REV 1.9
Nov / 2009
CONSUMER DRAM
©
NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG / NT5TU32M16CF
512Mb DDR2 SDRAM
Pin Configuration
–
60 balls BGA Package (x4, x8)
< TOP View>
See the balls through the package
x4
1
VDD
NC
VDDQ
NC
VDDL
2
NC
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA0
A10/AP
VSS
A3
A7
VDD
A12
3
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
NC
VDDQ
NC
VDD
ODT
x
1
VDD
DQ6
VDDQ
DQ4
VDDL
2
NU,/
RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA 0
A10/ AP
VSS
A3
A7
VDD
A12
3
VSS
DM/RDQS
VDDQ
DQ3
VSS
WE
BA 1
A1
A5
A9
NC
8
7
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
A
B
C
D
E
F
G
H
J
K
L
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
3
REV 1.9
Nov / 2009
CONSUMER DRAM
©
NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG / NT5TU32M16CF
512Mb DDR2 SDRAM
Pin Configuration
–
84 balls BGA Package (x16)
< TOP View>
See the balls through the package
x 16
1
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
2
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA0
A10/AP
VSS
A3
A7
VDD
A12
3
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
VSS
VDD
9
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
4
REV 1.9
Nov / 2009
CONSUMER DRAM
©
NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG / NT5TU32M16CF
512Mb DDR2 SDRAM
Input / Output Functional Description
Symbol
Type
Function
Clock:
CK and
C
are differential clock inputs. All address and control input signals are
CK,
C
Input
sampled on the crossing of the positive edge of CK and negative edge of
C.
Output
(read) data is referenced to the crossings of CK and
C
(both directions of crossing).
Clock Enable:
CKE high activates, and CKE low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE low provides Precharge
Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit and for
Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become
CKE
Input
stable during the power on and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry and exit, VREF must
maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK,
C,
ODT and CKE are disabled during Power
Down. Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select:
All commands are masked when
CS
is registered high.
CS
provides for
CS
Input
external rank selection on systems with multiple memory ranks.
of the command code.
RASCASE
Command Inputs:
RAS, CAS
and
E
(along with
CS)
define the command being
Input
entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write access. DM is
DM, LDM, UDM
Input
sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. For x8 device, the function of DM or RDQS /
RQDS
is enabled by EMRS command.
Bank Address Inputs:
BA# defines to which bank an Active, Read, Write or
BA0 – BA1
Input
Pre-charge command is being applied. Bank address also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provides the row address for Activate commands and the column
address and Auto Pre-charge or Read/Write commands to select one location out of
the memory array in the respective bank. A10 is sampled during a Pre-charge
A0 – A13
Input
command to determine whether the precharge applies to one bank (A10=low) or all
banks (A10=high). If only one bank is to be precharged, the bank is selected by
BA0-BA1. The address inputs also provide the op-code during Mode Register Set
commands.A13 Row address use on x4 and x8 components only.
DQ
Input/output
Data Inputs/Output:
Bi-directional data bus.
CS
is considered part
5
REV 1.9
Nov / 2009
CONSUMER DRAM
©
NANYA
TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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