PJDLLLC05
Low Capacitance TVS Diode Array
Signal(LVDS) ports.Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance, as
well as protect against over-voltage events as electrostatic discharges. The line-line concept minimizes the problems to
customers to re-route PCB lines, simplifying the design.
This diode array is configured to prote ct up to two high speed data tra nsmission lines, used in Low Voltage Differential
VOLTAGE
FEATURES
• Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground
• Maximum Leakage Current of 1.0uA @ V
RWM
• Industry Standard SMT Package SOT-563
• IEC61000-4-2 Full Compliance; 15kV air,8kV Contact
• 100% Tin Matte finish(LEAD-FREE PRODUCT)
•
Lead free in comply with EU RoHS 2002/95/EC directives.
• Green molding compound as per IEC61249 Std. . (Halogen Free)
SOT-563
0.011(0.27)
0.006(0.17)
Unit
：
inch(mm)
0.044(1.10)
0.035(0.90)
0.052(1.30)
0.043(1.10)
0.067(1.70)
0.059(1.50)
0.067(1.70)
0.059(1.50)
0.024(0.60)
0.019(0.50)
MECHANICAL DATA
• Case: SOT-563, Plastic
• Terminals:Solder plated,solderable per MIL-STD-750,Method2026
• Appox Weight : 0.0026 grams, 0.00009 ounces
0.007(0.17)
0.002(0.07)
APPLICATIONS
• USB 2.0 and Firewire Port Protection
• HDMI Version 1.3
• DVI
• Marking:05
0.012(0.30)
0.004(0.10)
Line-line concept ease the PCB design, directly placing the device over the data lines, opening only the contact points.
VREF is fixed by the operating voltage, referenced to the ground.
Note: pins 1and 6 (Line1), pins 3 and 4 (Line2) and pins 2 and 5 (Gnd) must be connected extemally, as the drawing
attached below.
MAXIMUM RATINGS (T
J
=25 C unless otherwise noted)
RATING
Peak Pulse Power (8/20μs Waveform)
Peak Pulse Current (8/20μs Waveform)
Operating Temperature Range
Storage Temperature Range
Soldering Temperature, t max=10s
SYMBOL
P
PP
I
PP
T
J
T
STG
T
L
VALUE
75
5
-55 to 125
-55 to 150
260
UNITS
W
A
o
O
C
C
C
o
o
May.23.2011-REV.01
PAGE . 1
PJDLLLC05
ELECTRICAL CHARACTERISTICS (T
J
=25 C unless otherwise noted)
PARAMETER
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20
μ
s)
Clamping Voltage (8/20
μ
s)
Clamping Voltage (8/20
μ
s)
Off State Junction Capacitance
SYMBOL
V
RWM
V
BR
I
R
o
CONDITIONS
-
I
BR
=1
mA
V
R
=5 V
I
I
I
P P
=1 A
P P
=2 A
P P
=5 A
MIN
-
6.2
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
MAX
5
-
1.0
10
12
15
1.2
0.6
UNITS
V
V
μA
V
C
V
C
V
C
C
J
V
V
V
pF
pF
0 V d c B i a s f=1 MHz
B e twe e n I/O p i ns a nd p i n GND
0 V d c B i a s f=1 MHz
B e twe e n I/O p i ns
ELECTRICAL CHARACTERISTIC CURVES
C
J
, Junction Capacitance (pF)
1
1000
V
R
= 5V
100
0.8
I/O to GND
0.6
0.4
0.2
0
0
1
2
3
4
5
I/O to I/O
I
R
,Leakge Current (nA)
10
1
25
50
75
100
125
150
V
R
, Reverse Bias Voltage (V)
T
J
, Junction Temperature (°C)
Fig.1 Typical Junction Capacitance
6
5
4
3
2
1
0
9
10
11
12
13
14
15
Fig.2 Typical Reverse Characteristics
I
PP
, Peak Pulse Current (A)
V
C
,Clamping Voltage (V)
Fig.3 Typical Peak Clamping Voltage (8/20μs)
May.23.2011-REV.01
Fig.4 8/20µs Peak Pulse Current Waveform
PAGE . 2
PJDLLLC05
MOUNTING PAD LAYOUT
SOT-563
Unit
：
inch(mm)
0.013
(0.34)
0.053
(1.35)
0.019
(0.50)
0.019
(0.50)
ORDER INFORMATION
• Packing information
T/R - 4K per 7" plastic Reel
T/R - 10K per 13" plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2012
The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.
May.23.2011-REV.01
0.017
(0.45)
PAGE . 3
Microchip MCU
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