LT4920C
Dual N-Channel 30-V Power MOSFET
GENERAL DESCRIPTION
The LT4920C is the N-Channel logic enhancement mode power field
effect transistors, using high cell density, DMOS trench technology.
This high density process is especially tailored to minimize on state
●
Exceptional on-resistance and maximum DC current
resistance.
These devices are particularly suited for low voltage application such
as cellular phone, notebook computer power management and other
battery powered circuits, and low in-line power loss that are needed
in a very small outline surface mount package.
capability
FEATURES
●
30V/6.9A, R
DS(ON)
=35 mΩ@VGS=10V
●
30V/5.8A, R
DS(ON)
=45 mΩ@VGS=4.5V
●
Super high density cell design for extremely low R
DS(ON)
APPLICATIONS
●
Power Management in Note book
●
Portable Equipment
●
Battery Powered System
●
DC/DC Converter
●
Load Switch
●
DSC
●
LCD Display inverter
PIN CONFIGURATION
(SOP-8)
Top View
Absolute Maximum Ratings
(T
A
=25℃ Unless Otherwise Noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current(tJ=150℃)
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
T
A
=25℃
Maximum Power Dissipation
Operating Junction Temperature
Thermal Resistance-Junction to Ambient
*
Thermal Resistance-Junction to Case
The *
*The device mounted on 1in FR4 board with 2 oz copper
2
Symbol
V
DSS
V
GSS
T
A
=25℃
T
A
=70℃
I
D
I
DM
I
S
P
D
T
J
R
θJA
Limit
30
±20
6.9
5.5
30
1.7
2
1.3
-55 to 150
T≦10 sec
Steady State
50
80
50
Unit
V
V
A
A
A
W
℃
℃/W
℃/W
T
A
=70℃
R
θJC
Rev 2. Nov. 2010
LT4920C
Dual N-Channel 30-V Power MOSFET
Electrical Characteristics
(T
A
=25℃ Unless Otherwise Specified)
Symbol
STATIC
V
GS(th)
I
GSS
Gate Threshold Voltage
Gate Leakage Current
V
DS
=V
GS
, I
D
=250μA
V
DS
=0V, V
GS
=±20V
V
DS
=30V, V
GS
=0V
I
DSS
Zero Gate Voltage Drain Current
a
Parameter
Limit
Min
1
Typ
1.4
Max
3
±100
1
Unit
V
nA
V
DS
=30V, V
GS
=0V
T
J
=55℃
μA
25
20
26
36
25
0.75
1.2
35
45
S
V
A
mΩ
I
D(ON)
R
DS(ON)
G
FS
V
SD
DYNAMIC
Qg
Qgs
Qgd
C
iss
C
oss
C
rss
t
d(on)
tr
t
d(off)
t
f
t
rr
Notes
On-State Drain Current
V
DS
≧
5V, V
GS
=10V
V
GS
=10V, I
D
= 6.9A
V
GS
=4.5V, I
D
= 5.8A
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
V
DS
=15V, I
D
=6.9A
I
S
=1.7A, V
GS
=0V
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Surce-Drain Reverse Recovery Time
I
F
=1.7A, di/dt=100A/μs
V
DD
=15V, R
L
=15Ω
I
D
=1A, V
GEN
=10V
R
G
=6Ω
V
DS
=15V, V
GS
=0V,
f=1MHz
V
DS
=15V, V
GS
=10V, I
D
=6.9A
11.5
2.7
2.3
350
65
16
9
10
32
3.5
50
15
nC
450
pF
12
23
40
5
90
ns
ns
a. Pulse test: pulse width≦ 300us, duty cycle≦ 2%, Guaranteed by design, not subject to production testing.
Rev 2. Nov. 2010
LT4920C
Dual N-Channel 30-V Power MOSFET
Typical Characteristics (T
J
=25℃ Noted)
℃
Rev 2. Nov. 2010
LT4920C
Dual N-Channel 30-V Power MOSFET
Typical Characteristics (T
J
=25℃ Noted)
℃
Rev 2. Nov. 2010
LT4920C
Dual N-Channel 30-V Power MOSFET
SOP-8 Package Outline
NOTES:
1. PKG ALL SURFACES ARE Ra0.8-1.2um.
2. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides).
Rev 2. Nov. 2010
FPGA/CPLD
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