NT5TU128M4AE(Green)
NT5TU64M8AE(Green)
NT5TU32M16AG(Green)
NT5TU128M4AB
NT5TU64M8AB
NT5TU64M8AF
NT5TU32M16AF
512Mb DDR2 SDRAM
Features
CAS Latency and Frequency
Speed Sorts
Bin
(CL-tRCD-TRP)
max. Clock
Frequency
Data Rate
CAS Latency
t
RCD
t
RP
t
RC
-5A
DDR2
-400
-37B
DDR2
-533
-3C
DDR2
-667
• Programmable Additive Latency: 0, 1, 2, 3 and 4
• Write Latency = Read Latency -1
Units
tck
MHz
Mb/s/pin
tck
ns
ns
ns
• Programmable Burst Length: 4 and 8
• Programmable Sequential / Interleave Burst
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• 4 bit prefetch architecture
• 1KB page size for x 4 & x 8,
2KB page size for x16
• Data-Strobes: Bidirectional, Differential
• Strong and Weak Strength Data-Output Driver
• Auto-Refresh and Self-Refresh
• Power Saving Power-Down modes
• 7.8 µs max. Average Periodic Refresh Interval
3-3-3
200
400
3
15
15
55
4-4-4
266
533
4
15
15
60
5-5-5
333
667
5
15
15
60
• 1.8V ± 0.1V Power Supply Voltage
• 4 internal memory banks
• Programmable CAS Latency: 3, 4 and 5
•
Packages:
60 pin BGA for x4/x8 components
84 pin BGA for x8/x16 components
Description
The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a high-
speed CMOS Double Data Rate 2 SDRAM containing
536,870,912 bits. It is internally configured as a quad-bank
DRAM.
The 512Mb chip is organized as either 32Mbit x 4 I/O x 4
bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank
device. These synchronous devices achieve high speed dou-
ble-data-rate transfer rates of up to 533 Mb/sec/pin for gen-
eral applications.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-
output driver, (4) variable data-output impedance adjustment
and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fash-
ion. A 16 bit address bus for x4 and x8 organised compo-
nents and a 15 bit address bus for x16 components is used to
convey row, column, and bank address devices.
These devices operate with a single 1.8V +/-0.1V power sup-
ply and are available in BGA packages.
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
REV 2.3
06/2008
1
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU128M4AE(Green)
NT5TU64M8AE(Green)
NT5TU32M16AG(Green)
NT5TU128M4AB
NT5TU64M8AB
NT5TU64M8AF
NT5TU32M16AF
512Mb DDR2 SDRAM
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE high activates and CKE low deactivates internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-
Refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE
are disabled during Self-Refresh.
Chip Select:
All command are masked when CS is registered high. CS provides for external rank
selection on systems with multiple memory ranks. CS is considered part of the command code.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM
and UDM are the input mask signals for x16 components and control the lower or upper bytes. For
x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1)
command.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provides the row address for Activate commands and the column address and
Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory
array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is
to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-
code during Mode Register Set commands.
Row address A13 is used on x4 and x8 components only.
Data Inputs/Output:
Bi-directional data bus.
Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on LDQ0 - LDQ7; UDQS corresponds
to the data on UDQ0-UDQ7. The data strobes DQS, LDQS, UDQS may be used in single ended
mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differen-
tial pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or
disables the complementary data strobe signals.
Read Data Strobe:
For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1)
for read timing. RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are
edge-aligned with read data. If RDQS, RDQS is enabled, the DM function is disabled on x8 com-
ponents.
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ,
DQS, DQS, RDQS, RDQS and DM for x8 configurations. For x16 configuration ODT is applied to
each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the
EMRS(1) is programmed to disable ODT.
No Connect:
No internal electrical connection is present.
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
1.8V +/- 0.1V
DQ Ground
DLL Power Supply:
1.8V +/- 0.1V
DLL Ground
Power Supply:
1.8V +/- 0.1V
Ground
SSTL_1.8 reference voltage
CKE
Input
CS
RAS, CAS, WE
Input
Input
DM, LDM, UDM
Input
BA0, BA1
Input
A0 - A13
Input
DQ
DQS, (DQS)
LDQS, (LDQS),
UDQS,(UDQS)
Input/Output
Input/Output
RDQS, (RDQS)
Input/Output
ODT
Input
NC
V
DDQ
V
SSQ
V
DDL
V
SSDL
V
DD
V
SS
V
REF
REV 2.3
06/2008
4
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
综合技术交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
