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RTL8201CP-VD: 产品描述Manchester Encoder/Decoder, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48; 产品类别无线/射频/通信电信电路; 文件大小581KB，共39页; 制造商瑞昱(REALTEK); 官网地址http://www.realtek.com.tw/; 瑞昱半导体成立于1987年，位于台湾「硅谷」的新竹科学园区，凭借当年几位年轻工程师的热情与毅力，走过艰辛的草创时期到今日具世界领导地位的专业IC设计公司，瑞昱半导体劈荆斩棘，展现旺盛的企图心与卓越的竞争力，开发出广受全球市场肯定与欢迎的高性能、高品质与高经济效益的IC解决方案。瑞昱半导体自成立以来一直保持稳定的成长，归功于瑞昱对产品/技术研发与创新的执着与努力，同时也归因于瑞昱的优良传统。

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RTL8201CP-VD概述

Manchester Encoder/Decoder, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48

RTL8201CP-VD规格参数

参数名称	属性值
厂商名称	瑞昱(REALTEK)
包装说明	LFQFP,
Reach Compliance Code	unknown
JESD-30 代码	S-PQFP-G48
长度	7 mm
功能数量	1
端子数量	48
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
座面最大高度	1.7 mm
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
电信集成电路类型	MANCHESTER ENCODER/DECODER
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
宽度	7 mm

RTL8201CP-VD文档预览

RTL8201CP

SINGLE-CHIP/SINGLE-PORT

10/100M FAST ETHERNET PHYCEIVER

(With Auto Crossover)

DATASHEET

Rev. 1.21

12 October 2004

Track ID: JATR-1076-21

RTL8201CP

Datasheet

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,

including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in

this document or in the product described in this document at any time. This document could include

technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document

are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the software engineer’s reference and provides detailed programming

information.

Though every effort has been made to ensure that this document is current and accurate, more information

may have become available subsequent to the production of this guide. In that event, please contact your

Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision

1.0

1.1

1.2

Release Date

2003/06/09

2003/09/26

2004/01/20

Summary

First release.

Minor cosmetic changes.

Modify LED Pin behavior.

Add LED multi-mode definition (7.5 LED and PHY Address

Configuration, page 19).

Add Power dissipation info (Table 31).

Bit <0:8> default setting changed to 0 (Table 9).

Bit <0:13> default setting changed to 0 (Table 9).

Bit <5:7> default setting changed to 0 (Table 14).

Bit <17:5> default setting changed to 1 (Table 17).

Bit <25:0> default setting changed to 0 (Table 20).

Bit <25:1> default setting changed to 0 (Table 20).

Bit <25:11~7> default setting changed to 00001 (Table 20).

Package additions. See section 10, Ordering Information, page 33.

1.21

2004/10/12

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

Track ID: JATR-1076-21 Rev. 1.21

RTL8201CP

Datasheet

Table of Contents

GENERAL DESCRIPTION................................................................................................................................................1

FEATURES...........................................................................................................................................................................1

BLOCK DIAGRAM.............................................................................................................................................................2

PIN ASSIGNMENTS ...........................................................................................................................................................3

PIN DESCRIPTION ............................................................................................................................................................4

5.1.

5.2.

5.3.

5.4.

5.5.

5.6.

5.7.

5.8.

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

6.7.

6.8.

6.9.

6.10.

6.11.

6.12.

7.1.

7.1.1.

7.1.2.

7.2.

7.2.1.

7.2.2.

7.2.3.

7.2.4.

7.3.

7.4.

7.5.

7.6.

7.7.

7.8.

7.8.1.

7.8.2.

7.8.3.

7.9.

7.10.

7.11.

MII I

NTERFACE

............................................................................................................................................................4

SNI (S

ERIAL

ETWORK

NTERFACE

) 10M

BPS

NLY

....................................................................................................5

LOCK

NTERFACE

.......................................................................................................................................................5

10M

BPS

/100M

BPS

ETWORK

NTERFACE

....................................................................................................................5

EVICE

ONFIGURATION

NTERFACE

...........................................................................................................................6

LED I

NTERFACE

/PHY A

DDRESS

ONFIGURATION

.......................................................................................................6

OWER AND

ROUND

INS

..........................................................................................................................................7

ESET AND

THER

INS

...............................................................................................................................................7

EGISTER

0 B

ASIC

ODE

ONTROL

EGISTER

............................................................................................................8

EGISTER

1 B

ASIC

ODE

TATUS

EGISTER

...............................................................................................................9

EGISTER

2 PHY I

DENTIFIER

EGISTER

1 ...................................................................................................................9

EGISTER

3 PHY I

DENTIFIER

EGISTER

2 ...................................................................................................................9

EGISTER

4 A

UTO

-N

EGOTIATION

DVERTISEMENT

EGISTER

(ANAR) ....................................................................10

EGISTER

5 A

UTO

-N

EGOTIATION

INK

ARTNER

BILITY

EGISTER

(ANLPAR)......................................................10

EGISTER

6 A

UTO

-N

EGOTIATION

XPANSION

EGISTER

(ANER) .............................................................................11

EGISTER

16 NW

ETUP

EGISTER

(NSR) ............................................................................................................12

EGISTER

17 L

OOPBACK

, B

YPASS

, R

ECEIVER

RROR

ASK

EGISTER

(LBREMR) ................................................12

EGISTER

18 RX_ER C

OUNTER

(REC).....................................................................................................................13

EGISTER

19 SNR D

ISPLAY

EGISTER

......................................................................................................................13

EGISTER

25 T

EST

EGISTER

.....................................................................................................................................13

MII

AND

ANAGEMENT

NTERFACE

..........................................................................................................................14

Data Transition.....................................................................................................................................................14

Serial Management...............................................................................................................................................15

UTO

-N

EGOTIATION AND

ARALLEL

ETECTION

......................................................................................................16

Setting the Medium Type and Interface Mode to MAC.........................................................................................16

UTP Mode and MII Interface ...............................................................................................................................16

UTP Mode and SNI Interface ...............................................................................................................................17

Fiber Mode and MII Interface..............................................................................................................................17

LOW

ONTROL

UPPORT

..........................................................................................................................................17

ARDWARE

ONFIGURATION AND

UTO

-N

EGOTIATION

............................................................................................18

LED

AND

PHY A

DDRESS

ONFIGURATION

................................................................................................................19

ERIAL

ETWORK

NTERFACE

....................................................................................................................................20

OWER

OWN

, L

INK

OWN

, P

OWER

AVING

AND

SOLATION

ODES

......................................................................20

EDIA

NTERFACE

.....................................................................................................................................................20

100Base-TX ..........................................................................................................................................................20

100Base-FX Fiber Mode Operation.....................................................................................................................21

10Base-T TX/RX ...................................................................................................................................................21

EPEATER

ODE

PERATION

.....................................................................................................................................22

ESET

AND

RANSMIT

IAS

......................................................................................................................................22

3.3V P

OWER

UPPLY AND

OLTAGE

ONVERSION

IRCUIT

.......................................................................................22

iii

Track ID: JATR-1076-21 Rev. 1.21

REGISTER DESCRIPTIONS ............................................................................................................................................8

FUNCTIONAL DESCRIPTION.......................................................................................................................................14

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

RTL8201CP

Datasheet

7.12.

8.1.

8.1.1.

8.1.2.

8.1.3.

8.1.4.

8.2.

8.2.1.

8.2.2.

8.2.3.

8.2.4.

8.2.5.

8.3.

8.4.

10.

9.1.

AULT

NDICATION

......................................................................................................................................22

DC C

HARACTERISTICS

...............................................................................................................................................23

Absolute Maximum Ratings ..................................................................................................................................23

Operating Conditions ...........................................................................................................................................23

Power Dissipation ................................................................................................................................................23

Input Voltage: Vcc ................................................................................................................................................23

AC C

HARACTERISTICS

...............................................................................................................................................24

MII Transmission Cycle Timing............................................................................................................................24

MII Reception Cycle Timing .................................................................................................................................25

SNI Transmission Cycle Timing............................................................................................................................27

SNI Reception Cycle Timing .................................................................................................................................28

MDC/MDIO Timing..............................................................................................................................................29

RYSTAL

HARACTERISTICS

......................................................................................................................................30

RANSFORMER

HARACTERISTICS

............................................................................................................................30

ECHANICAL

IMENSIONS

OTES

............................................................................................................................32

ORDERING INFORMATION......................................................................................................................................33

CHARACTERISTICS .......................................................................................................................................................23

MECHANICAL DIMENSIONS .......................................................................................................................................31

List of Tables

Table 1. MII Interface..................................................................................................................................4

Table 2. SNI (Serial Network Interface) 10Mbps Only ..............................................................................5

Table 3. Clock Interface ..............................................................................................................................5

Table 4. 10Mbps/100Mbps Network Interface............................................................................................5

Table 5. Device Configuration Interface .....................................................................................................6

Table 6. LED Interface/PHY Address Configuration..................................................................................6

Table 7. Power and Ground Pins .................................................................................................................7

Table 8. Reset and Other Pins......................................................................................................................7

Table 9. Register 0 Basic Mode Control Register .......................................................................................8

Table 10. Register 1 Basic Mode Status Register..........................................................................................9

Table 11. Register 2 PHY Identifier Register 1.............................................................................................9

Table 12. Register 3 PHY Identifier Register 2.............................................................................................9

Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)..................................................10

Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) ....................................10

Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) .........................................................11

Table 16. Register 16 NWay Setup Register (NSR)....................................................................................12

Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) ..............................12

Table 18. Register 18 RX_ER Counter (REC)............................................................................................13

Table 19. Register 19 SNR Display Register ..............................................................................................13

Table 20. Register 25 Test Register.............................................................................................................13

Table 21. Serial Management ......................................................................................................................15

Table 22. Setting the Medium Type and Interface Mode to MAC..............................................................16

Table 23. UTP Mode and MII Interface ......................................................................................................16

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

Track ID: JATR-1076-21 Rev. 1.21

RTL8201CP

Datasheet

Table 24. UTP Mode and SNI Interface......................................................................................................17

Table 25. Fiber Mode and MII Interface .....................................................................................................17

Table 26. Auto-Negotiation Mode Pin Settings ..........................................................................................18

Table 27. LED Definitions ..........................................................................................................................19

Table 28. Power Saving Mode Pin Settings ................................................................................................20

Table 29. Absolute Maximum Ratings........................................................................................................23

Table 30. Operating Conditions...................................................................................................................23

Table 31. Power Dissipation........................................................................................................................23

Table 32. Input Voltage: Vcc.......................................................................................................................23

Table 33. MII Transmission Cycle Timing .................................................................................................24

Table 34. MII Reception Cycle Timing.......................................................................................................25

Table 35. SNI Transmission Cycle Timing .................................................................................................27

Table 36. SNI Reception Cycle Timing ......................................................................................................28

Table 37. MDC/MDIO Timing....................................................................................................................29

Table 38. Crystal Characteristics.................................................................................................................30

Table 39. Transformer Characteristics ........................................................................................................30

Table 40. Ordering Information...................................................................................................................33

List of Figures

Figure 1. Block Diagram .............................................................................................................................2

Figure 2. Pin Assignments...........................................................................................................................3

Figure 3. Read Cycle .................................................................................................................................15

Figure 4. Write Cycle ................................................................................................................................15

Figure 5. LED and PHY Address Configuration.......................................................................................19

Figure 7. MII Transmission Cycle Timing-1.............................................................................................24

Figure 8. MII Transmission Cycle Timing-2.............................................................................................25

Figure 9. MII Reception Cycle Timing-1 ..................................................................................................26

Figure 10. MII Reception Cycle Timing-2 ..................................................................................................26

Figure 11. SNI Transmission Cycle Timing-1 ............................................................................................27

Figure 12. SNI Transmission Cycle Timing-2 ............................................................................................27

Figure 13. SNI Reception Cycle Timing-1..................................................................................................28

Figure 14. SNI Reception Cycle Timing-2..................................................................................................28

Figure 15. MDC/MDIO Timing ..................................................................................................................29

Figure 16. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................29

Figure 17. MDC/MDIO PHY to MAC Reception Without Error ...............................................................30

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

Track ID: JATR-1076-21 Rev. 1.21

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