RTL8201F-VB-CG
RTL8201FL-VB-CG
RTL8201FN-VB-CG
SINGLE-CHIP/PORT 10/100M ETHERNET
PHYCEIVER WITH AUTO MDIX
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.4
30 November 2011
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
ii
Track ID: JATR-2265-11
Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
REVISION HISTORY
Revision Release Date Summary
1.0
2010/12/17 First release.
1.1
2011/02/18 Revised to VB model.
Revised Table 22 Register 30 Interrupt Indicators and SNR Display Register, page 21.
Added interrupt function.
Added MMD Register Mapping and Definition section.
Revised section 8.2 Interrupt, page 31.
Revised Table 46 Absolute Maximum Ratings, page 44.
Revised 9.1.3 Power On and PHY Reset Sequence, page 45.
Revised Table 49 RMII Input Mode Power Dissipation (Whole System), page 46.
1.2
2011/04/21 Revised Figure 2 Block Diagram, page 4.
Revised Table 3 RMII Interface, page 10.
Revised Table 7 Device Configuration Interface, page 11.
Revised Table 9 Reset and Other Pins, page 14.
Revised Table 11 Register 0 Basic Mode Control Register, page 15.
Revised Table 15 Register 4 Auto-Negotiation Advertisement Register (ANAR), page 17.
Revised Table 20 Register 24, page 20.
Revised Table 24 Page4 Register 16 EEE Capability Enable Register, page 22.
Revised Table 25 Page4 Register 21 EEE Capability Register, page 22.
Revised Table 30 Page7 Register 19 , page 24.
Added section 7.21 Page 7 Register 24 Spread Spectrum Clock Register, page 25.
Revised section 8.1.2 Serial Management Interface, page 29.
Revised section 8.7 Reset and Transmit Bias, page 38.
Added section 8.13 Spread Spectrum Clock (SSC), page 43.
Added Figure 21 MII Interface Setup/Hold Time Definitions, page 47.
Added Figure 26 RMII Interface Setup, Hold Time, and Output Delay Time Definitions,
page 49.
Added Figure 28 MDC/MDIO Interface Setup, Hold Time, and Valid from MDC Rising Edge
Time Definitions, page 51.
1.3
2011/07/14 Added Figure 1 Application Diagram, page 3.
Revised Table 30 Page7 Register 19 Interrupt, WOL Enable, and LEDs Function Registers,
page 24.
Added Table 34 EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00), page 25.
Added Table 35 EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01), page 26.
Added section 8.4.1 LED and PHY Address, page 32.
Added section 8.4.8 EEE LED, page 36.
Revised section 8.7 Reset and Transmit Bias, page 38.
1.4
2011/11/30 Revised Figure 2 Block Diagram, page 4.
Revised Table 4 Clock Interface, page 10 (CKXTAL2 pin revised from I to IO).
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
iii
Track ID: JATR-2265-11
Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ..............................................................................................................................................1
FEATURES .........................................................................................................................................................................2
APPLICATIONS ................................................................................................................................................................3
3.1.
A
PPLICATION
D
IAGRAM
...............................................................................................................................................3
BLOCK DIAGRAM ...........................................................................................................................................................4
PIN ASSIGNMENTS .........................................................................................................................................................5
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
6.
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
RTL8201F (32-P
IN
).....................................................................................................................................................5
G
REEN
P
ACKAGE AND
V
ERSION
I
DENTIFICATION
........................................................................................................5
RTL8201FL (48-P
IN
) ..................................................................................................................................................6
G
REEN
P
ACKAGE AND
V
ERSION
I
DENTIFICATION
........................................................................................................6
RTL8201FN (48-P
IN
)..................................................................................................................................................7
G
REEN
P
ACKAGE AND
V
ERSION
I
DENTIFICATION
........................................................................................................7
MII I
NTERFACE
............................................................................................................................................................8
S
ERIAL
M
ANAGEMENT
I
NTERFACE
............................................................................................................................10
RMII I
NTERFACE
.......................................................................................................................................................10
C
LOCK
I
NTERFACE
.....................................................................................................................................................10
10M
BPS
/100M
BPS
N
ETWORK
I
NTERFACE
.................................................................................................................11
T
RANSMIT
B
IAS
R
EFERENCE
......................................................................................................................................11
D
EVICE
C
ONFIGURATION
I
NTERFACE
........................................................................................................................11
P
OWER AND
G
ROUND
P
INS
........................................................................................................................................13
R
ESET AND
O
THER
P
INS
.............................................................................................................................................14
NC (N
OT
C
ONNECTED
) P
INS
......................................................................................................................................14
PIN DESCRIPTIONS.........................................................................................................................................................8
REGISTER DESCRIPTIONS.........................................................................................................................................15
7.1.
R
EGISTER
0 B
ASIC
M
ODE
C
ONTROL
R
EGISTER
..........................................................................................................15
7.2.
R
EGISTER
1 B
ASIC
M
ODE
S
TATUS
R
EGISTER
.............................................................................................................16
7.3.
R
EGISTER
2 PHY I
DENTIFIER
R
EGISTER
1..................................................................................................................17
7.4.
R
EGISTER
3 PHY I
DENTIFIER
R
EGISTER
2..................................................................................................................17
7.5.
R
EGISTER
4 A
UTO
-N
EGOTIATION
A
DVERTISEMENT
R
EGISTER
(ANAR) ...................................................................17
7.6.
R
EGISTER
5 A
UTO
-N
EGOTIATION
L
INK
P
ARTNER
A
BILITY
R
EGISTER
(ANLPAR)....................................................18
7.7.
R
EGISTER
6 A
UTO
-N
EGOTIATION
E
XPANSION
R
EGISTER
(ANER) ............................................................................19
7.8.
P
AGE
0 R
EGISTER
13 MACR (MMD A
CCESS
C
ONTROL
R
EGISTER
; A
DDRESS
0
X
0D) ...............................................20
7.9.
P
AGE
0 R
EGISTER
14 MAADR (MMD A
CCESS
A
DDRESS
D
ATA
R
EGISTER
; A
DDRESS
0
X
0E)...................................20
7.10.
R
EGISTER
24 P
OWER
S
AVING
M
ODE
R
EGISTER
(PSMR) ...........................................................................................20
7.11.
R
EGISTER
28 F
IBER
M
ODE AND
L
OOPBACK
R
EGISTER
...............................................................................................21
7.12.
R
EGISTER
30 I
NTERRUPT
I
NDICATORS AND
SNR D
ISPLAY
R
EGISTER
........................................................................21
7.13.
R
EGISTER
31 P
AGE
S
ELECT
R
EGISTER
.......................................................................................................................21
7.14.
P
AGE
4 R
EGISTER
16 EEE C
APABILITY
E
NABLE
R
EGISTER
.......................................................................................22
7.15.
P
AGE
4 R
EGISTER
21 EEE C
APABILITY
R
EGISTER
.....................................................................................................22
7.16.
P
AGE
7 R
EGISTER
16 RMII M
ODE
S
ETTING
R
EGISTER
(RMSR) ................................................................................22
7.17.
P
AGE
7 R
EGISTER
17 C
USTOMIZED
LED
S
S
ETTING
R
EGISTER
...................................................................................23
7.18.
P
AGE
7 R
EGISTER
18 EEE LED
S
E
NABLE
R
EGISTER
.................................................................................................23
7.19.
P
AGE
7 R
EGISTER
19 I
NTERRUPT
, WOL E
NABLE
,
AND
LED
S
F
UNCTION
R
EGISTERS
................................................24
7.20.
P
AGE
7 R
EGISTER
20 MII TX I
SOLATE
R
EGISTER
......................................................................................................25
7.21.
P
AGE
7 R
EGISTER
24 S
PREAD
S
PECTRUM
C
LOCK
R
EGISTER
......................................................................................25
7.22.
MMD R
EGISTER
M
APPING AND
D
EFINITION
.............................................................................................................25
7.22.1.
EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) .............................................................25
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
iv
Track ID: JATR-2265-11
Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.22.2.
7.22.3.
7.22.4.
7.22.5.
7.22.6.
8.
EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01) ................................................................26
EEECR (EEE Capability Register, MMD Device 3; Address 0x14)................................................................26
EEEWER (EEE Wake Error Register, MMD Device 3; Address 0x16) ..........................................................26
EEEAR (EEE Advertisement Register, MMD Device 7; Address 0x3c) ..........................................................27
EEELPAR (EEE Link Partner Ability Register, MMD Device 7; Address 0x3d) ............................................27
FUNCTIONAL DESCRIPTION.....................................................................................................................................28
8.1.
MII
AND
M
ANAGEMENT
I
NTERFACE
..........................................................................................................................29
8.1.1. Data Transition ....................................................................................................................................................29
8.1.2. Serial Management Interface ...............................................................................................................................29
8.2.
I
NTERRUPT
.................................................................................................................................................................31
8.3.
A
UTO
-N
EGOTIATION AND
P
ARALLEL
D
ETECTION
.....................................................................................................31
8.3.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................31
8.4.
LED F
UNCTIONS
........................................................................................................................................................32
8.4.1. LED and PHY Address .........................................................................................................................................32
8.4.2. Link Monitor.........................................................................................................................................................32
8.4.3. RX LED ................................................................................................................................................................33
8.4.4. TX LED.................................................................................................................................................................33
8.4.5. TX/RX LED...........................................................................................................................................................34
8.4.6. LINK/ACT LED ....................................................................................................................................................34
8.4.7. Customized LED...................................................................................................................................................35
8.4.8. EEE LED Behavior...............................................................................................................................................36
8.5.
P
OWER
D
OWN AND
L
INK
D
OWN
P
OWER
S
AVING
M
ODES
..........................................................................................36
8.6.
10M/100M T
RANSMIT AND
R
ECEIVE
.........................................................................................................................37
8.6.1. 100Base-TX Transmit and Receive Operation .....................................................................................................37
8.6.2. 100Base-FX Fiber Transmit and Receive Operation ...........................................................................................37
8.6.3. 10Base-T Transmit and Receive Operation..........................................................................................................37
8.7.
R
ESET AND
T
RANSMIT
B
IAS
.......................................................................................................................................38
8.8.
3.3V P
OWER
S
UPPLY AND
V
OLTAGE
C
ONVERSION
C
IRCUIT
......................................................................................38
8.9.
A
UTOMATIC
P
OLARITY
C
ORRECTION
........................................................................................................................39
8.10.
F
AR
E
ND
F
AULT
I
NDICATION
.....................................................................................................................................39
8.11.
W
AKE
-O
N
-LAN (WOL)............................................................................................................................................39
8.11.1.
Magic Packet and Wake-Up Frame Format....................................................................................................39
8.11.2.
Active Low Wake-On-LAN...............................................................................................................................40
8.11.3.
Pulse Low Wake-On-LAN................................................................................................................................41
8.11.4.
Wake-On-LAN Pin Types (MII Mode) .............................................................................................................42
8.11.5.
Wake-On-LAN Pin Types (RMII Mode)...........................................................................................................42
8.12.
E
NERGY
E
FFICIENT
E
THERNET
(EEE)........................................................................................................................43
8.13.
S
PREAD
S
PECTRUM
C
LOCK
(SSC) .............................................................................................................................43
9.
CHARACTERISTICS......................................................................................................................................................44
9.1.
DC C
HARACTERISTICS
...............................................................................................................................................44
9.1.1. Absolute Maximum Ratings ..................................................................................................................................44
9.1.2. Recommended Operating Conditions ...................................................................................................................44
9.1.3. Power On and PHY Reset Sequence.....................................................................................................................45
9.1.4. RMII Input Mode Power Dissipation ...................................................................................................................46
9.1.5. Input Voltage: Vcc................................................................................................................................................46
9.2.
AC C
HARACTERISTICS
...............................................................................................................................................47
9.2.1. MII Transmission Cycle Timing ...........................................................................................................................47
9.2.2. MII Reception Cycle Timing.................................................................................................................................48
9.2.3. RMII Transmission and Reception Cycle Timing .................................................................................................49
9.2.4. MDC/MDIO Timing .............................................................................................................................................51
9.2.5. Transmission without Collision ............................................................................................................................52
9.2.6. Reception without Error .......................................................................................................................................52
9.3.
C
RYSTAL
C
HARACTERISTICS
.....................................................................................................................................53
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
v
Track ID: JATR-2265-11
Rev. 1.4
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