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RTL8139C-LF: 产品描述Micro Peripheral IC; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小714KB，共67页; 制造商瑞昱(REALTEK); 官网地址http://www.realtek.com.tw/; 瑞昱半导体成立于1987年，位于台湾「硅谷」的新竹科学园区，凭借当年几位年轻工程师的热情与毅力，走过艰辛的草创时期到今日具世界领导地位的专业IC设计公司，瑞昱半导体劈荆斩棘，展现旺盛的企图心与卓越的竞争力，开发出广受全球市场肯定与欢迎的高性能、高品质与高经济效益的IC解决方案。瑞昱半导体自成立以来一直保持稳定的成长，归功于瑞昱对产品/技术研发与创新的执着与努力，同时也归因于瑞昱的优良传统。

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RTL8139C-LF概述

Micro Peripheral IC

RTL8139C-LF规格参数

参数名称	属性值
厂商名称	瑞昱(REALTEK)
包装说明	,
Reach Compliance Code	unknown

RTL8139C-LF文档预览

RTL8139C

RTL8139C-LF

RTL8139CL

RTL8139CL-LF

3.3V SINGLE-CHIP FAST ETHERNET

CONTROLLER WITH POWER MANAGEMENT

DATASHEET

Rev. 1.6

29 December 2005

Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com.tw

RTL8139C(L)

Datasheet

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,

including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in

this document or in the product described in this document at any time. This document could include

technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are

trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek

RTL8139C(L) chip.

Though every effort has been made to ensure that this document is current and accurate, more information

may have become available subsequent to the production of this guide. In that event, please contact your

Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision

1.5

Release Date

2005/11/28

1.6

2005/12/29

Summary

Format and layout changes.

Add package ID information (Section 4.1 Package and Version

Identification, page 4).

Add ordering information (Section 14 Ordering Information, page 63).

Add sentence “Writing a 1 to any bit will reset that bit, but writing a 0 has no

effect” to section 6.6 Interrupt Status Register (Offset 003Eh-003Fh, R/W),

page 14.

3.3V Single-Chip Fast Ethernet Controller w/Power Management

Track ID: JATR-1076-21 Rev. 1.6

RTL8139C(L)

Datasheet

Table of Contents

General Description .............................................................................................................................................................1

Features.................................................................................................................................................................................2

Block Diagram ......................................................................................................................................................................3

Pin Assignments....................................................................................................................................................................4

4.1. Package and Version Identification................................................................................................................................4

5. Pin Descriptions....................................................................................................................................................................5

5.1. Power Management/Isolation Interface..........................................................................................................................5

5.2. PCI Interface ..................................................................................................................................................................5

5.3. FLASH/EEPROM Interface...........................................................................................................................................7

5.4. Power Pins......................................................................................................................................................................8

5.5. LED Interface.................................................................................................................................................................8

5.6. Attachment Unit Interface ..............................................................................................................................................8

5.7. Test and Other Pins ........................................................................................................................................................8

6. Register Descriptions ...........................................................................................................................................................9

6.1. Receive Status Register in Rx Packet Header ..............................................................................................................11

6.2. Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) .................................................................................12

6.3. ERSR: Early Rx Status Register (Offset 0036h, R) .....................................................................................................13

6.4. Command Register (Offset 0037h, R/W).....................................................................................................................13

6.5. Interrupt Mask Register (Offset 003Ch-003Dh, R/W).................................................................................................14

6.6. Interrupt Status Register (Offset 003Eh-003Fh, R/W).................................................................................................14

6.7. Transmit Configuration Register (Offset 0040h-0043h, R/W) ....................................................................................15

6.8. Receive Configuration Register (Offset 0044h-0047h, R/W)......................................................................................16

6.9. 9346CR: 93C46 (93C56) Command Register (Offset 0050h, R/W)............................................................................19

6.10.

CONFIG 0: Configuration Register 0 (Offset 0051h, R/W) ....................................................................................19

6.11.

CONFIG 1: Configuration Register 1 (Offset 0052h, R/W) ....................................................................................20

6.12.

Media Status Register (Offset 0058h, R/W).............................................................................................................21

6.13.

CONFIG 3: Configuration Register3 (Offset 0059h, R/W) .....................................................................................21

6.14.

CONFIG 4: Configuration Register4 (Offset 005Ah, R/W) ....................................................................................23

6.15.

Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) .............................................................................24

6.16.

PCI Revision ID (Offset 005Eh, R)..........................................................................................................................24

6.17.

Transmit Status of All Descriptors (TSAD) Register (Offset 0060h-0061h, R/W) .................................................24

6.18.

Basic Mode Control Register (Offset 0062h-0063h, R/W)......................................................................................25

6.19.

Basic Mode Status Register (Offset 0064h-0065h, R) .............................................................................................25

6.20.

Auto-Negotiation Advertisement Register (Offset 0066h-0067h, R/W)..................................................................26

6.21.

Auto-Negotiation Link Partner Ability Register (Offset 0068h-0069h, R)..............................................................27

6.22.

Auto-Negotiation Expansion Register (Offset 006Ah-006Bh, R)............................................................................27

6.23.

Disconnect Counter (Offset 006Ch-006Dh, R) ........................................................................................................27

6.24.

False Carrier Sense Counter (Offset 006Eh-006Fh, R)............................................................................................28

6.25.

NWay Test Register (Offset 0070h-0071h, R/W)....................................................................................................28

6.26.

RX_ER Counter (Offset 0072h-0073h, R)...............................................................................................................28

6.27.

CS Configuration Register (Offset 0074h-0075h, R/W)..........................................................................................28

6.28.

Flash Memory Read/Write Register (Offset 00D4h-00D7h, R/W)..........................................................................29

6.29.

Config5: Configuration Register 5 (Offset 00D8h, R/W) ........................................................................................29

6.30.

Function Event Register (Offset 00F0h-00F3h, R/W) .............................................................................................30

6.31.

Function Event Mask Register (Offset 00F4h-00F7h, R/W) ...................................................................................31

6.32.

Function Present State Register (Offset 00F8h-00FBh, R) ......................................................................................31

6.33.

Function Force Event Register (Offset 00FCh-00FFh, W) ......................................................................................32

7. EEPROM Contents (93C46 or 93C56).............................................................................................................................33

7.1. Summary of EEPROM Registers .................................................................................................................................35

7.2. Summary of EEPROM Power Management Registers ................................................................................................35

8. PCI Configuration Space Registers ..................................................................................................................................36

8.1. PCI Configuration Space Table....................................................................................................................................36

3.3V Single-Chip Fast Ethernet Controller w/Power Management

iii

Track ID: JATR-1076-21 Rev. 1.6

RTL8139C(L)

Datasheet

8.2. PCI Configuration Space Functions .............................................................................................................................38

8.3. Default Values After Power-on (RSTB asserted) ........................................................................................................42

8.3.1.

PCI Configuration Space Table............................................................................................................................42

8.4. PCI Power Management Functions ..............................................................................................................................44

8.5. Vital Product Data (VPD) ............................................................................................................................................46

9. Functional Description.......................................................................................................................................................47

9.1. Transmit Operation.......................................................................................................................................................47

9.2. Receive Operation ........................................................................................................................................................47

9.3. Line Quality Monitor....................................................................................................................................................47

9.4. Clock Recovery Module...............................................................................................................................................47

9.5. Loopback Operation.....................................................................................................................................................47

9.6. Tx Encapsulation..........................................................................................................................................................47

9.7. Collision .......................................................................................................................................................................47

9.8. Rx Decapsulation .........................................................................................................................................................48

9.9. Flow Control ................................................................................................................................................................48

9.9.1.

Control Frame Transmission ................................................................................................................................48

9.9.2.

Control Frame Reception .....................................................................................................................................48

9.10.

LED Functions .........................................................................................................................................................49

9.10.1. 10/100Mbps Link Monitor ...................................................................................................................................49

9.10.2. LED_RX...............................................................................................................................................................49

9.10.3. LED_TX...............................................................................................................................................................49

9.10.4. LED_TX+LED_RX .............................................................................................................................................50

10. Application Diagram..........................................................................................................................................................51

11. Electrical Characteristics...................................................................................................................................................52

11.1.

Temperature Limit Ratings.......................................................................................................................................52

11.2.

DC Characteristics....................................................................................................................................................52

11.2.1. Supply Voltage .....................................................................................................................................................52

11.3.

AC Characteristics....................................................................................................................................................53

11.3.1. FLASH/BOOT ROM Timing...............................................................................................................................53

11.3.2. PCI Bus Operation Timing...................................................................................................................................55

12. Mechanical Dimensions (128-Pin QFP)............................................................................................................................61

13. Mechanical Dimensions (128-Pin LQFP) .........................................................................................................................62

14. Ordering Information ........................................................................................................................................................63

3.3V Single-Chip Fast Ethernet Controller w/Power Management

Track ID: JATR-1076-21 Rev. 1.6

RTL8139C(L)

Datasheet

General Description

The Realtek RTL8139C(L) is a highly integrated and cost-effective single-chip Fast Ethernet controller

that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u

100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports Advanced

Configuration Power management Interface (ACPI), PCI power management for modern operating

systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most

efficient power management possible. The RTL8139CL is suitable for applications such as CardBus or

mobile devices with a built-in network controller. The CIS data can be stored in either a 93C56 EEPROM

or expansion ROM.

In addition to the ACPI feature, the RTL8139C(L) also supports remote wake-up (including AMD Magic

Packet, LinkChg, and Microsoft wake-up frame) in both ACPI and APM environments. The RTL8139C(L)

is capable of performing an internal reset through the application of auxiliary power. When auxiliary power

is on and the main power remains off, the RTL8139C(L) is ready and waiting for the Magic Packet or Link

Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active

high, active low, positive pulse, and negative pulse. The versatility of the RTL8139C(L) LWAKE pin

provides motherboards with the Wake-On-LAN (WOL) function. The RTL8139C(L) also supports Analog

Auto-Power-down, that is, the analog part of the RTL8139C(L) can be shut down temporarily according to

user requirements or when the RTL8139C(L) is in a power down state with the wakeup function disabled.

In addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then

both the analog and digital parts stop functioning and power consumption of the RTL8139C(L) will be

negligible. The RTL8139C(L) also supports an auxiliary power auto-detect function, and will

auto-configure related bits of their own PCI power management registers in PCI configuration space.

The PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies

hardware (i.e., the RTL8139C(L) LAN card). The information may consist of part number, serial number,

and other detailed information.

To provide cost down support, the RTL8139C(L) is capable of using a 25MHz crystal or OSC as its internal

clock source.

The RTL8139C(L) keeps network maintenance costs low and eliminates usage barriers. It is the easiest way

to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps

bandwidth possible at no additional cost. To improve compatibility with other brands’ products, the

RTL8139C(L) is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The

RTL8139C(L) is highly integrated and requires no “glue” logic or external memory. It includes an interface

for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of

management.

3.3V Single-Chip Fast Ethernet Controller w/Power Management

Track ID: JATR-1076-21 Rev. 1.6

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