NT512D64S8HC0G / NT256D64S88C0G
NT512D64S8HC0GY / NT256D64S88C0GY (Green)
512MB and 256MB
PC3200 and PC2700
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
Based on DDR400/333 256M bit C Die device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 256M bit die C device,
organized as either 32Mx8 or 16Mx16
• Performance:
PC3200 PC2700
Speed Sort
DIMM
CAS
Latency
f
CK
t
CK
f
DQ
Clock Frequency
Clock Cycle
DQ Burst Frequency
5T
3
200
5
400
6K
2.5
166
6
333
MHz
ns
MHz
Unit
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2/2.5(6K), 2.5/3(5T)
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts
• SDRAMs are packaged in TSOP packages
• Intended for 166 and 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= V
DDQ
= 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
Description
NT512D64S8HC0G, NT512D64S8HC0GY, NT256D64S88C0G, and NT256D64S88C0GY are unbuffered 184-Pin Double Data Rate
(DDR) Synchronous DRAM Dual In-Line Memory Modules (DIMM). NT512D64S8HC0G and NT512D64S8HC0GY are DDR 512MB
modules organized as dual ranks using sixteen 32Mx8 TSOP devices. NT256D64S88C0G and NT256D64S88C0GY are DDR 256MB
modules organized as single rank using eight 32Mx8 TSOP devices.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation
type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The unbuffered DDR DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect
implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by
JEDEC.
REV 1.0
March 31, 2004
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512D64S8HC0G / NT256D64S88C0G
NT512D64S8HC0GY / NT256D64S88C0GY (Green)
Unbuffered DDR DIMM
Ordering Information
Part Number
NT512D64S8HC0G-5T
64Mx64
NT512D64S8HC0GY-5T
NT256D64S88C0G-5T
32Mx64
NT256D64S88C0GY-5T
Gold
NT512D64S8HC0G -6K
64Mx64
NT512D64S8HC0GY -6K
NT256D64S88C0G -6K
32Mx64
NT512D64S8HC0GY -6K
Green
DDR333
Devices
PC2700
2.5-3-3
Green
166MHz (6ns @ CL = 2.5)
2.5V
Green
DDR400
Devices
PC3200
3-3-3
Green
200MHz (5ns @ CL = 3)
2.6V
Organization
Speed
Power
Leads
Note
For the closest sales office or information, please visit:
www.nanya.com
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
REV 1.0
March 31, 2004
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512D64S8HC0G / NT256D64S88C0G
NT512D64S8HC0GY / NT256D64S88C0GY (Green)
Unbuffered DDR DIMM
Pin Description
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0-A9, A11, A12
A10/AP
BA0, BA1
V
REF
V
DDID
Differential Clock Inputs.
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-precharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
DQ0-DQ63
DQS0-DQS7
DM0-DM7
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bidirectional data strobes
Input Data Mask
Power
Supply voltage for DQs
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
CK1
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
V
SS
DQ4
DQ5
V
DDQ
DM0/DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DM1/DQS10
V
DD
DQ14
DQ15
CKE1
V
DDQ
NC
DQ20
A12
V
SS
DQ21
A11
DM2/DQS11
V
DD
DQ22
A8
DQ23
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
KEY
53
54
55
56
57
58
59
60
61
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
Front
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
NC
A0
NC
V
SS
NC
BA1
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
KEY
145
146
147
148
149
150
151
152
153
V
SS
DQ36
DQ37
V
DD
DM4/DQS13
DQ38
DQ39
V
SS
DQ44
Back
V
SS
A6
DQ28
DQ29
V
DDQ
DM3/DQS12
A3
DQ30
V
SS
DQ31
NC
NC
V
DDQ
CK0
CK0
V
SS
NC
A10
NC
V
DDQ
NC
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
V
DDQ
WE
DQ41
CAS
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
CK2
CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
WP
SDA
SCL
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
V
DDQ
S0
S1
DM5/DQS14
V
SS
DQ46
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DM6/DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DM7/DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.0
March 31, 2004
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512D64S8HC0G / NT256D64S88C0G
NT512D64S8HC0GY / NT256D64S88C0GY (Green)
Unbuffered DDR DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
Type
(SSTL)
Polarity
Cross
point
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
S0, S1
(SSTL)
Active
Low
Active
Low
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
RAS, CAS, WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
Supply
Supply
(SSTL)
-
When sampled at the positive rising edge of the clock,
RAS, CAS, WE
define the operation to
be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
A0 - A9
A10/AP
A11, A12
when sampled at the rising clock edge. In addition to the column address, AP is used to
(SSTL)
-
invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63
DQS0 - DQS7,
DQS9 – DQS16
CB0 – CB7
DM0 – DM8
V
DD
, V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
Supply
(SSTL)
(SSTL)
(SSTL)
Input
Supply
-
-
-
-
Active
High
-
Active
High
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the Serial
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
(SSTL)
REV 1.0
March 31, 2004
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512D64S8HC0G / NT256D64S88C0G
NT512D64S8HC0GY / NT256D64S88C0GY (Green)
Unbuffered DDR DIMM
Functional Block Diagram
512MB, 2 Ranks, 16 devices, 32Mx8 DDR SDRAMs
S1
S0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQS4
DM4/DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0-BA1
A0-A13
RAS
CAS
CKE0
CKE1
WE
Notes :
1.
2.
3.
4.
BA0-BA1 : SDRAMs D0-D15
A0-A13 : SDRAMs D0-D15
RAS
: SDRAMs D0-D15
CAS
: SDRAMs D0-D15
CKE : SDRAMs D0-D7
CKE : SDRAMs D8-D15
WE
: SDRAMs D0-D15
V
DDSPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
Serial PD
SCL
WP
A0
SA0
A1
SA1
SPD
D0-D15
D0-D15
D0-D15
Strap: see Note 4
* Clock Wiring
Clock Input
SDRAMs
*CK0/CK0
4 SDRAMs
*CK1/CK1
6 SDRAMs
*CK2/CK2
6 SDRAMs
* Wire per Clock Loading Table/
Wiring Diagrams
A2
SA2
SDA
DQ-to-I/O wiring is shown as recommended but may be changed.
DQ/DQS/DM/CKE/S relationships must be maintained as shown.
DQ, DQS, DM/DQS resistors: 22 Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.0
March 31, 2004
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
