NT2GTT64U88B0UN / NT2GTT64U88B0US
2GB : 256M x 64
PC2-4200/PC2-5300/PC26400 Unbuffered DDR2 SO-DIMM
200 pin Unbuffered DDR2 SO-DIMM
Based on 2x128Mx8 (Stacking) DDR2 SDRAM
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 256Mx64 Unbuffered DDR2 SO-DIMM based on 2 ranks of
128Mx8 DDR2 SDRAM device.
• Performance:
PC2-4200 PC2-5300 PC2-6400
Speed Sort
DIMM
f
CK
t
CK
f
DQ
Latency
Clock Frequency
Clock Cycle
DQ Burst Frequency
37B
4
266
3.75
533
3C
5
333
3
667
25D
6
400
2.5
800
MHz
ns
MHz
Unit
• Intended for 266MHz, 333MHz and 400MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8V ± 0.1V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
Latency: 3, 4, 5 (-37B/-3C); 4, 5, 6 (-25D)
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 71-ball stacked BGA Package
• RoHS Compliance
• Halogen free - NT2GTT64U88B0US
Description
NT2GTT64U88B0UN and NT2GTT64U88B0US are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline
Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 256Mx64 high-speed memory array. Modules use eight 256Mx8
(2x128Mx8) 71-ball stacked BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as
reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM
DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.
The DIMM is intended for use in applications operating up to 266MHz (333MHz or 400MHz) clock speeds and achieves high-speed data
transfer rates of up to 533MHz (667MHz or 800 MHz). Prior to any access operation, the device
latency and burst/length/operation
type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
Speed
Organization
Power
Leads
Note
NT2GTT64U88B0UN –37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
NT2GTT64U88B0UN –3C
NT2GTT64U88B0US –3C
NT2GTT64U88B0UN –25D
NT2GTT64U88B0US –25D
DDR2-667 PC2-5300 333MHz (3.0ns @ CL = 5)
256Mx64
1.8V
Gold
Green
DDR2-800 PC2-6400 400MHz (2.5ns @ CL =6)
REV 1.3
10/2007
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GTT64U88B0UN / NT2GTT64U88B0US
2GB : 256M x 64
PC2-4200/PC2-5300/PC26400 Unbuffered DDR2 SO-DIMM
Pin Description
CK0-CK1
-
CKE0, CKE1
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
,
A0-A9, A11-A13
A10/AP
BA0, BA1
ODT0, ODT1
NC
Chip Selects
Address Inputs
Column Address Input/Auto-precharge
SDRAM Bank Address Inputs
Active termination control lines
No Connect
DQ0-DQ63
DQS0-DQS7
-
DM0-DM7
V
DD
V
REF
V
DDSPD
V
SS
SCL
SDA
SA0, SA1
Data input/output
Bidirectional data strobes
Differential data strobes
Input Data Masks
Power (1.8V)
Ref. Voltage for SSTL_18 inputs
Serial EEPROM positive power supply
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
Front
V
REF
V
SS
DQ0
DQ1
V
SS
Pin Back
2
4
6
8
V
SS
DQ4
DQ5
V
SS
Pin Front
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
Back
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
V
DD
Front
A1
V
DD
A10/AP
BA0
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
DQS5
V
SS
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Back
A0
V
DD
BA1
Pin Front
151 DQ42
153 DQ43
155 V
SS
157 DQ48
159 DQ49
161 V
SS
163 NC
165 V
SS
167
169 DQS6
171 V
SS
173 DQ50
175 DQ51
177 V
SS
179 DQ56
181 DQ57
183 V
SS
185 DM7
187 V
SS
189 DQ58
191 DQ59
193 V
SS
195 SDA
197 SCL
199 V
DDSPD
Pin Back
152 DQ46
154 DQ47
156 V
SS
158 DQ52
160 DQ53
162 V
SS
164 CK1
166
168 V
SS
170 DM6
172 V
SS
174 DQ54
176 DQ55
178 V
SS
180 DQ60
182 DQ61
184 V
SS
186
188 DQS7
190 V
SS
192 DQ62
194 DQ63
196 V
SS
198 SA0
200 SA1
10 DM0
12 V
SS
14 DQ6
16 DQ7
18 V
SS
20 DQ12
22 DQ13
24 V
SS
26 DM1
28 V
SS
30 CK0
32
34 V
SS
36 DQ14
38 DQ15
40 V
SS
42 V
SS
44 DQ20
46 DQ21
48 V
SS
50 NC
100 A2
REV 1.3
10/2007
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GTT64U88B0UN / NT2GTT64U88B0US
2GB : 256M x 64
PC2-4200/PC2-5300/PC26400 Unbuffered DDR2 SO-DIMM
Input/Output Functional Description
Symbol
CK0-CK1,
-
Type
(SSTL)
(SSTL)
Polarity
Cross
Point
Active
High
Active
Low
Active
Low
Active
High
-
Function
The system clock inputs. All the DDR2 SDRAM address and control inputs are sampled on
the cross point of the rising edge of CK and falling edge of
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs.
On-Die Termination control signals.
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A13 defines the row address when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 – A13 defines the column address
when sampled at the rising clock edge. In addition to the column address, A10/AP is used
to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is
high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is
low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Data strobe for input and output data.
Positive
Edge
Active
High
-
-
-
Supply
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if it
is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
CKE0, CKE1
(SSTL)
,
V
REF
,
(SSTL)
Supply
Input
(SSTL)
,
,
define the operation
ODT0, ODT1
BA0 - BA2
A0 - A9
A10/AP
A11 - A13
(SSTL)
-
DQ0 – DQ63
V
DD
,
V
SS
DQS0 – DQS7
–
(SSTL)
Supply
(SSTL)
Active
High
DM0 – DM7
Input
SA0 – SA2
SDA
SCL
V
DDSPD
REV 1.3
10/2007
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GTT64U88B0UN / NT2GTT64U88B0US
2GB : 256M x 64
PC2-4200/PC2-5300/PC26400 Unbuffered DDR2 SO-DIMM
Functional Block Diagram
(2GB, 2Ranks, x8 DDR2 SDRAMs)
REV 1.3
10/2007
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GTT64U88B0UN / NT2GTT64U88B0US
2GB : 256M x 64
PC2-4200/PC2-5300/PC26400 Unbuffered DDR2 SO-DIMM
Serial Presence Detect
(Part 1 of 2)
SPD Entry Value
Byte
Description
PC2-4200
-37B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Ranks
Data Width of Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=5
DDR2 SDRAM Device Access Time from Clock at CL=5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes: CAS Latencies Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes:
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=4
Maximum Data Access Time from Clock at CL=4
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time from Clock at CL=3
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock (t
IS
)
Address and Command Hold Time After Clock (t
IH
)
Data Input Setup Time Before Clock (t
DS
)
Data Input Hold Time After Clock (t
DH
)
Write Recovery Time (t
WR
)
Internal Write to Read Command delay (t
WTR
)
Internal Read to Precharge delay (t
RTP
)
Reserved
Extension of Byte 41 t
RC
and Byte 42 t
RFC
Minimum Core Cycle Time (t
RC
)
0.25ns
0.375ns
0.225ns
0.10ns
0.175ns
15.0ns
7.5ns
7.5ns
Undefined
The number below a decimal point of
tRC=0 and tRFC=5, tRFC is less than
256ns
60.0ns
06
3C
5,4,3
<3.80mm
Regular SODIMM (67.6mm)
Normal DIMM
Support weak driver
/50ohm ODT/ PASR
3.75ns
±0.5ns
5.0ns
±0.6ns
15ns
7.5ns
15ns
45.0
1GB
0.2ns
0.275ns
0.17ns
0.25
0.05ns
0.12ns
22
25
37
10
17
3C
1E
1E
00
00
3ns
±0.45ns
3.75ns
±0.5ns
3D
50
50
60
3C
1E
3C
2D
01
20
27
17
25
05
12
3.75ns
±0.5ns
PC2-5300
-3C
128
256
DDR2
15
10
2 rank, Height=30mm
64
Undefined
SSTL_1.8V
3ns
±0.45ns
Non parity/ECC
7.8µs/self
X8
N/A
Undefined
4,8
8
6,5,4
38
01
04
00
07
30
45
3D
50
2.5ns
±0.4ns
3D
50
Serial PD Data Entry
(Hexadecimal)
-25D
-37B
-3C
80
08
08
0E
0A
71
40
00
05
30
45
00
82
08
00
00
0C
08
70
25
40
-25D
PC2-6400 PC2-4200 PC2-5300 PC2-6400
Note
REV 1.3
10/2007
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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