NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
Based on DDR3-1066/1333 256Mx8 SDRAM B-Die
Features
•Performance:
Speed Sort
DIMM CAS Latency
fck – Clock Frequency
tck – Clock Cycle
fDQ – DQ Burst Frequency
PC3-8500
-BE
7
533
1.875
1066
PC3-10600
-CG
9
667
1.5
1333
MHz
ns
Mbps
• Programmable Operation:
- DIMM
Latency: 6,7,8,9, 11
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 15/10/1 (row/column/rank) Addressing for 2GB
• 15/10/2 (row/column/rank) Addressing for 4GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance and Halogen free
Unit
• 240-Pin Dual In-Line Memory Module (UDIMM)
• 256Mx72 and 512Mx72 DDR3 Unbuffered DIMM with ECC based
on 256Mx8 DDR3 SDRAM B-Die devices.
• Intended for 533MHz/667MHz applications
•V
DD
= V
DDQ
= 1.5V ± 0.075V (for DDR3)
•V
DD
= V
DDQ
= 1.35V -0.0675/+0.1V (for DDR3L)
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Nominal and Dynamic On-Die Termination support
Description
NT2GC72B89B0NF / NT4GC72B8PB0NF / NT2GC72C89B0NF / NT4GC72C8PB0NF / NT2GC72C89B2NF and NT4GC72C8PB2NF are
240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module with ECC (UDIMM w/ ECC), organized
as one rank of 256Mx72 (2GB) and two ranks of 512Mx72 (4GB) high-speed memory array. Modules use nine 256Mx8 (2GB) 78-ball BGA
packaged devices and eighteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards
developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device
latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A14 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.1
10/2010
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
Ordering Information
Part Number
NT2GC72B89B0NF-BE
NT2GC72B89B0NF-CG
NT4GC72B8PB0NF-BE
NT4GC72B8PB0NF-CG
NT2GC72C89B0NF-BE
NT2GC72C89B0NF-CG
NT2GC72C89B2NF-CG
NT4GC72C8PB0NF-BE
NT4GC72C8PB0NF-CG
NT4GC72C8PB2NF-CG
DDR3-1066
DDR3-1333
DDR3-1066
DDR3-1333
DDR3-1066
DDR3-1333
DDR3-1333
DDR3-1066
DDR3-1333
DDR3-1333
Speed
PC3-8500
533MHz (1.875ns @ CL = 7)
256Mx72
PC3-10600 667MHz (1.5ns @ CL = 9)
1.5V
PC3-8500
533MHz (1.875ns @ CL = 7)
512Mx72
PC3-10600 667MHz (1.5ns @ CL = 9)
PC3-8500
533MHz (1.875ns @ CL = 7)
256Mx72
1.35V
PC3-8500
533MHz (1.875ns @ CL = 7)
512Mx72
PC3-10600 667MHz (1.5ns @ CL = 9)
PC3-10600 667MHz (1.5ns @ CL = 9)
Gold
Gold
Organization
Power
Leads
Note
PC3-10600 667MHz (1.5ns @ CL = 9)
PC3-10600 667MHz (1.5ns @ CL = 9)
Pin Description
Pin Name
CK0, CK1
,
CKE0, CKE1
,
A0-A9, A11, A14
A10/AP
A12/
BA0-BA2
ODT0, ODT1
SCL
SDA
Description
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-Precharge
Address Input/Burst Chop
SDRAM Bank Address Inputs
Active termination control lines
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Pin Name
DQ0-DQ63
DQS0-DQS8
-
DM0-DM8
CB0-CB7
V
REFDQ
, V
REFCA
V
DDSPD
SA0, SA1
Vtt
V
SS
V
DD
NC
Data strobes
Data strobes complement
Data Masks
ECC Check Bits
Temperature event pin
Reset pin
Input/Output Reference
SPD and Temp sensor power
Serial Presence Detect Address Inputs
Termination voltage
Ground
Core and I/O power
No Connect
Description
Data input/output
REV 1.1
10/2010
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
DDR3 SDRAM Pin Assignment
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Front
V
REFDQ
V
SS
DQ0
DQ1
V
SS
Pin
121
122
123
124
125
Back
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ25
V
SS
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
V
SS
CB2
CB3
V
SS
NC
NC
CKE0
V
DD
BA2
NC
V
DD
A11
A7
V
DD
A5
A4
V
DD
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
NC
CKE1/NC
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
A2
V
DD
CK1/NC
/NC
V
DD
V
DD
V
REFCA
NC
V
DD
A10/AP
BA0
V
DD
V
DD
ODT1/NC
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
A1
V
DD
V
DD
CK0
V
DD
Pin
91
92
93
94
95
96
Front
DQ41
V
SS
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
126
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
97
A0
V
DD
BA1
V
DD
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
V
DD
NC
NC
V
DD
A12/
A9
V
DD
A8
A6
V
DD
A3
Note: CK1,
,
CKE1,
and ODT1 are for 2GB modules only.
REV 1.1
10/2010
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
Input/Output Functional Description
Symbol
CK0, CK1
,
CKE0, CKE1
,
,
,
ODT0, ODT1
DM0 – DM8
Type
Input
Input
Polarity
Cross
point
Active
High
Active
Low
Active
Low
Active
High
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of
.
A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by
;
Rank 1 is selected by
When sampled at the positive rising edge of CK and falling edge of
,
signals
,
,
define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and
signals if enabled via the DDR3 SDRAM
mode register.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
signals are complements, and timing is relative to the cross point of respective DQS and
.
If the module is to be operated in single ended strobe mode, all
signals must be tied on
the system board to V
SS
and DDR3 SDRAM mode registers programmed appropriately.
Selects which DDR3 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of
.
During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
.
In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
Data Input/Output pins.
Check bits are used for ECC
-
-
-
-
-
-
-
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a pull
up.
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The
pin is reserved for use to flag critical module temperature.
This signal resets the DDR3 SDRAM
Input
Input
Input
Input
DQS0 – DQS8
–
I/O
Cross
point
BA0, BA1, BA2
Input
-
A0 – A9
A10/AP
A11
A12/
A13
Input
-
DQ0 – DQ63
CB0 – CB7
V
DD
,
V
DDSPD,
V
SS
V
REFDQ,
V
REFCA
SDA
SCL
SA0 – SA2
Input
-
I/O
Supply
Supply
I/O
Input
Input
Output
Input
REV 1.1
10/2010
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
Functional Block Diagram
[2GB
–
1 Rank, 256Mx8 DDR3 SDRAMs]
DQS0
DM0
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4
DM4
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
D0
D4
ZQ
ZQ
DQS1
DM1
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
DQS5
DM5
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
D1
D5
ZQ
ZQ
DQS2
DM2
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
DQS6
DM6
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
D2
D6
ZQ
ZQ
DQS3
DM3
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
DQS7
DM7
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
D3
D7
ZQ
ZQ
DQS8
DM8
DM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS
D8
V
DDSPD
V
DD
/V
DDQ
V
REFDQ
V
SS
V
REFCA
BA0-BA2
A0-A13
CKE0
ODT0
CK0
SDA
ZQ
SCL
SA0
SA1
SCL
A0
A1
A2
Temp Sensor
DDR3
SDRAM
SPD
D0-D8
D0-D8
D0-D8
D0-D8
BA0-BA2: SDRAMs D0-D8
A0-A13: SDRAMs D0-D8
:
SDRAMs D0-D8
:
SDRAMs D0-D8
CKE: SDRAMs D0-D8
:
SDRAMs D0-D8
ODT: SDRAMs D0-D8
CK: SDRAMs D0-D8
:
SDRAMs D0-D8
:
SDRAMs D0-D8
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω
±1%.
CKE0, A[13:0],
, , ,
ODT0, BA[2:0],
DDR3
SDRAM
CK
V
TT
V
DD
REV 1.1
10/2010
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
微控制器 MCU
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