PJSMDA05-6 SERIES
HEX TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 6 TVS/Zener Array family have been designed to Protect Sensitive
Equipment against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5V, 12V, 15V and 24V. This TVS array offers an integrated
solution to protect up to 6 data lines where the board space is a premium.
P
SPECIFICATION FEATURES
1
8
7 GND
6 GND
5
SOIC-8
350W Power Dissipation (8x20µsec Waveform)
Low Leakage Current, Maximum of 5µA at rated voltage
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Packaged in the Industry Standard SOIC-8
2
3
4
APPLICATIONS
RS-232C or RS-422 Communication ports
GPIB/IEEE 485 Ports
Portable Instrumentation
5
8
1
4
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8x20µsec Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P
pp
V
ESD
TJ
T
stg
Value
350
>25
-50 to +125
-50 to +150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device)
Tj = 25°C
PJSMDA05-6
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
cl
V
cl
Cj
Cj
I
BR
= 1mA
V
R
= 5V
I pp = 5A
I pp = 24A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
5 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
Conditions
Min
Typical
Max
5
Units
V
V
6
5
9.8
13
225
125
µA
V
V
pF
pF
7/1/2009
Page
1
www.panjit.com
PJSMDA05-6 SERIES
ELECTRICAL CHARACTERISTICS (Per Device)
Tj = 25°C
PJSMDA12-6
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
cl
V
cl
Cj
I
BR
= 1mA
V
R
= 12V
I pp = 5A
I pp = 15A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
Conditions
Min
Typical
Max
12
Units
V
V
P
13.3
5
20
25
100
µA
V
V
pF
PJSMDA15-6
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
cl
V
cl
Cj
I
BR
= 1mA
V
R
= 15V
I pp = 5A
I pp = 12A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
Conditions
Min
Typical
Max
15
Units
V
V
16.7
5
24
29
80
µA
V
V
pF
PJSMDA24-6
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
cl
V
cl
Cj
I
BR
= 1mA
V
R
= 24V
I pp = 5A
I pp = 8A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
Conditions
Min
Typical
Max
24
Units
V
V
26.7
5
40
44
60
µA
V
V
pF
7/1/2009
Page 2
www.panjit.com
PJSMDA05-6 SERIES
TYPICAL CHARACTERISTICS
TJ = 25°C unless otherwise noted
Surge Pulse Waveform Definition
N
on-R
epetitive Peak Pulse Power vs Pulse Time
Peak Pulse Power - Ppp (W)
110
100
90
80
70
60
50
40
30
20
10
0
0
Pulse Waveform
1000
50% of Ipp @ 20µs
100
10
1
0.1
0.01
1
10
100
1000
Pulse D
uration, µsec
Percent of Ipp
Rise time 10-90% - 8µs
5
10
15
tim e, µsec
20
25
30
Clamping Voltage vs. Peak current
Off-State Capacitance per Device - 1MHz
PJSMDAxx-6
45
40
35
30
25
20
15
10
5
0
0
5
Clamping voltage, V
PJS 24
MS
PJSMDAxx-6
200
180
160
140
120
100
80
60
40
20
0
0
05
PJSMS05
24
PJS
15
MS
15
PJS
12
MS
12
05
PJS 05
MS
Capacitance, pF
PJSMS1
2
12
15
5
PJSMS1
24
PJSMS24
10
15
20
25
30
1
2
3
4
5
Ipp, A (8/20µsec)
Bias, Vdc
7/1/2009
Page 3
www.panjit.com
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
