NT5DS128M4AF
NT5DS64M8AF
NT5DS32M16AF
512Mb DDR SDRAM
Features
CAS Latency and Frequency
Maximum Operating Frequency
(MHz)*
DDR333
DDR266B
(-6K)
*
(-75B)
2
133
100
2.5
166
133
*
-6K also meets DDR266A Spec
(MHz-CL-t
RCD
-t
RP
= 133-2-3-3)
CAS
Latency
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Burst lengths: 2, 4, or 8
CAS Latency: 2, 2.5
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8µs Maximum Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
V
DDQ
= 2.5V
±
0.2V
V
DD
= 2.5V
±
0.2V
-6K Speed sort: Supports PC2700/PC2100 modules
-75B Speed sort: Supports PC2100 modules
Description
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a
2n
prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 512Mb
DDR SDRAM effectively consists of a single
2n-bit
wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.
REV 1.0
06/2003
1
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS128M4AF
NT5DS64M8AF
NT5DS32M16AF
512Mb DDR SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
128 X 4
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ3
NC
DQ2
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ0
NC
DQ1
QFC
NC
WE
RAS
BA1
A0
A2
VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
64 X 8
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
QFC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
REV 1.0
06/2003
2
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS128M4AF
NT5DS64M8AF
NT5DS32M16AF
512Mb DDR SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
32 X 16
1
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
2
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ13
DQ11
DQ9
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ2
DQ4
DQ6
LDQS
LDW
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
REV 1.0
06/2003
3
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS128M4AF
NT5DS64M8AF
NT5DS32M16AF
512Mb DDR SDRAM
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.
Chip Select:
All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
Data Input/Output:
Data bus.
Data Strobe:
Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-
DQ7; UDQS corresponds to the data on DQ8-DQ15
No Connect:
No internal electrical connection is present.
Electrical connection is present. Should not be connected at second level of assembly.
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
2.5V
±
0.2V.
DQ Ground
Power Supply:
2.5V
±
0.2V.
Ground
SSTL_2 reference voltage:
(V
DDQ
/ 2)
±
1%.
CKE, CKE0, CKE1
Input
CS, CS0, CS1
Input
RAS, CAS , WE
Input
DM
Input
BA0, BA1
Input
A0 - A12
Input
DQ
DQS, LDQS, UDQS
NC
NU
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Input/Output
Input/Output
REV 1.0
06/2003
4
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS128M4AF
NT5DS64M8AF
NT5DS32M16AF
512Mb DDR SDRAM
Ordering Information
Speed
Org.
Part Number
NT5DS128M4AF-6K
128M x 4
NT5DS128M4AF-75B
NT5DS64M8AF-6K
64M x 8
NT5DS64M8AF-75B
NT5DS32M16AF-6K
32M x 16
NT5DS32M16AF-75B
Package
Clock (MHz)
60ball BGA
0.8mmx1.0mm
Pitch
60ball BGA
0.8mmx1.0mm
Pitch
60ball BGA
0.8mmx1.0mm
Pitch
166
133
166
133
166
133
CL-t
RCD
-t
RP
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
Clock (MHz)
133
100
133
100
133
100
CL-t
RCD
-t
RP
2-3-3
2-2-2
2-3-3
2-2-2
2-3-3
2-2-2
DDR333/DDR266A
DDR266B
DDR333/DDR266A
DDR266B
DDR333/DDR266A
DDR266B
Comments
Note:
1. At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information only
REV 1.0
06/2003
5
©
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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