NT5SV8M16FS-6K/75B
NT5SV8M16FT-6K/75B
128Mb Synchronous DRAM
Features
•
•
•
•
•
•
•
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BS0/BS1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, Full page
Programmable Wrap: Sequential or Interleave
Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
•
•
•
•
•
•
Dual Data Mask for byte control (x16)
Auto Refresh and Self Refresh
64ms refresh period (4K cycle)
JEDEC standard 3.3V Power Supply
LVTTL compatible
Package: 54-pin TSOP (II)
Description
The NT5SV8M16FS and NT5SV8M16FT are four-bank Syn-
chronous DRAMs organized as 1Mbit x 16 I/O x 4 Bank.
These synchronous devices achieve high-speed data trans-
fer rates of up to 166MHz by employing a pipeline chip archi-
tecture that synchronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eight col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A7, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
ation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.
REV 1.0
09/2006
1
The Document is a general product description and is subject to change without notice.
NT5SV8M16FS-6K/75B
NT5SV8M16FT-6K/75B
128Mb Synchronous DRAM
Pin Assignments for Planar Components
(Top View)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
54-pin Plastic TSOP(II)
REV 1.0
09/2006
2
The Document is a general product description and is subject to change without notice.
NT5SV8M16FS-6K/75B
NT5SV8M16FT-6K/75B
128Mb Synchronous DRAM
Pin Description
CLK
CKE
CS
RAS
CAS
WE
BS1, BS0
A0 - A11
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power supply
Ground
Output Power for DQs
Ground for DQs
No Connection
—
Input/Output Functional Description
Symbol
CLK
CKE
CS
RAS, CAS,
WE
BS0, BS1
Type
Input
Input
Input
Input
Input
Polarity
Positive
Edge
Active High
Active Low
Active Low
—
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS enables the command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA7) when sampled
at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, auto-
precharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s)
to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low,
then BS0 and BS1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
A0 - A11
Input
—
DQ0 - DQ15
LDQM
UDQM
V
DD
, V
SS
V
DDQ
V
SSQ
Input-
Output
Input
Supply
Supply
—
Active High
—
—
REV 1.0
09/2006
3
The Document is a general product description and is subject to change without notice.
NT5SV8M16FS-6K/75B
NT5SV8M16FT-6K/75B
128Mb Synchronous DRAM
Ordering Information
Organization
Part Number
N2SV12816FT-6K
8M x 16
N2SV12816FT-75B
N2SV12816FS-6K
N2SV12816FS-75B
Speed Grade
Clock Frequency@CAS Latency
166MHz@CL3
133MHz@CL3
166MHz@CL3
133MHz@CL3
Power
Supply
3.3 V
Package
54-PIN
TSOP II
54-PIN
TSOP II Green
3.3 V
REV 1.0
09/2006
4
The Document is a general product description and is subject to change without notice.
NT5SV8M16FS-6K/75B
NT5SV8M16FT-6K/75B
128Mb Synchronous DRAM
Absolute Maximum Ratings
Symbol
V
DD
V
DDQ
V
IN
V
OUT
T
A
T
STG
P
D
I
OUT
Parameter
Power Supply Voltage
Power Supply Voltage for Output
Input Voltage
Output Voltage
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
Short Circuit Output Current
Rating
-1.0 to +4.6
-1.0 to +4.6
-1.0 to +4.6
-1.0 to +4.6
0 to +70
-55 to +150
1.0
50
Units
V
V
V
V
°C
°C
W
mA
Notes
1
1
1
1
1
1
1
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
(T
A
= 0°C to 70°C)
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
OH
V
OL
Parameter
Supply Voltage
Supply Voltage for Output
Input High Voltage
Input Low Voltage
Output Level (LVTTL)
Output “H” Level Voltage
Output Level (LVTTL)
Output “L” Level Voltage (
Rating
Min.
3.0
3.0
2.0
-0.3
2.4
—
Typ.
3.3
3.3
3.0
0
—
—
Max.
3.6
3.6
V
DD
+ 0.3
0.8
—
0.4
Units
V
V
V
V
V
V
1
2
I
OH
= -2.0mA
I
OL
= 2.0mA
Notes
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The overshoot voltage duration is
≤
3ns.
Capacitance
(T
A
= 23°C, f = 1MHz, V
DD
= 3.3V, V
REF
=1.4+/-200mV )
Symbol
C
IN
C
ADD
C
CLK
C
OUT
Parameter
Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM)
Address
Input Clock (CLK)
Output Capacitance (DQ0 - DQ15)
Min.
2.5
2.5
2.5
4.0
64Mb
Max.
5.0
5.0
4.0
6.5
128Mb
Max.
3.8
3.8
3.5
6.0
Units
pF
pF
pF
pF
REV 1.0
09/2006
5
The Document is a general product description and is subject to change without notice.
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