NT2GT64U8HB0JY
2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
240pin Unbuffered DDR2 SDRAM MODULE
Based on 128Mx8 DDR2 SDRAM B-die
Features
Performance:
Speed Sort
DIMM
Latency
t
CK
Clock Cycle
f
DQ
DQ Burst Frequency
*
PC2-4200
-37B
4
266
3.75
533
PC2-5300
-3C
5
333
3
667
PC2-6400
-25D
6
400
2.5
800
MHz
ns
MHz
- Device
Latency: 4(-37B), 5 (-3C) and 6 (-25D)
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 14/10/2 Addressing (row/column/rank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• On Die Termination (ODT)
• Gold contacts
• SDRAMs in 68-ball BGA Package
• RoHs Compliance
Unit
f
CK
Clock Frequency
• JEDEC Standard 240-pin Dual In-Line Memory Module
• 256Mx64 DDR2 Unbuffered DIMM based on 128Mx8 DDR2
SDRAM B-die
• Intended for 266MHz/333MHz/400MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8Volt ± 0.1
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
• Address and control signals are fully synchronous to positive
clock edge
• Write Latency = Read Latency - 1
• Programmable Operation:
Description
NT2GT64U8HB0JY is 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM),
organized as a two ranks 256Mx64 high-speed memory array. Modules use sixteen 128Mx8 DDR2 SDRAMs in BGA packages. These
DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files
minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface
in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 400MHz clock speeds and achieves high-speed data transfer rates of up to
800MHz. Prior to any access operation, the device
latency and burst / length /operation type must be programmed into the DIMM by
address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.1
09/2007
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT2GT64U8HB0JY
2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Ordering Information
Part Number
NT2GT64U8HB0JY-37B
NT2GT64U8HB0JY-3C
NT2GT64U8HB0JY-25D
Speed
266MHz (3.75ns @ CL = 4)
333MHz (3.00ns @ CL = 5)
400MHz (2.50ns @ CL = 6)
DDR2-533
DDR2-667
DDR2-800
PC2-4200
PC2-5300
PC2-6400
256Mx64
GOLD
1.8V
Organization
Leads
Power
Note
Pin Description
CK0~CK2
CKE0, CKE1
,
A0 ~ A13
~
BA0 ~ BA2
RESET
ODT0, ODT1
NC
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address bus
DIMM Rank Select
SDRAM Bank Address Inputs
Reset pin
On-die termination control lines
No Connect
DQ0-DQ63
DQS0-DQS8
DM0-DM8
-
V
DD
V
REF
V
DDSPD
V
SS
SCL
SDA
SA0 ~ SA2
Data input/output
Bidirectional data strobes
Input Data Mask
Differential data strobes
Power (1.8V)
Ref. Voltage for SSTL_18 inputs
Serial EEPROM positive power supply
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
REV 1.1
09/2007
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT2GT64U8HB0JY
2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
V
SS
DQ26
DQ27
V
SS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
KEY
V
SS
V
SS
V
DD
NC
V
DD
A10/AP
BA0
V
DDQ
V
DDQ
ODT1
V
DDQ
V
SS
DQ32
DQ33
Front
NC
NC
V
SS
DQS8
V
SS
NC
NC
V
SS
V
DDQ
CKE0
V
DD
BA2
NC
V
DDQ
A11
A7
V
DD
A5
A4
V
DDQ
A2
V
DD
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
V
SS
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Back
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
KEY
CK0
V
DD
A0
V
DD
BA1
V
DDQ
V
DDQ
ODT0
A13
V
DD
V
SS
DQ36
DQ37
V
SS
Back
NC
V
SS
DM8
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE1
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
V
DDQ
A3
A1
V
DD
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
REV 1.1
09/2007
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT2GT64U8HB0JY
2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2
, ,
CKE0, CKE1
Type
(SSTL)
(SSTL)
(SSTL)
Polarity
Function
The positive line of the differential pair of system clock inputs which drives the input to
Positive
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
Edge
rising edge of their associated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to
Edge the on-DIMM PLL.
Active
High
Active
Low
Active
Low
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
When sampled at the positive rising edge of the clock,
,
,
define the
operation to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Active
High
-
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR SDRAM input buffers and core logic
Negative
and
Data strobe for input and output data
Positive
Edge
Active
High
-
-
-
Supply
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
,
,
,
V
REF
V
DDQ
ODT0, ODT1
BA0 – BA2
(SSTL)
(SSTL)
Supply
Supply
Input
(SSTL)
A0 - A9
A10/AP
A11 - A13
(SSTL)
-
DQ0 – DQ63
V
DD,
V
SS
DQS0 – DQS8
–
(SSTL)
Supply
(SSTL)
Active
High
DM0 – DM8
Input
SA0 – SA2
SDA
SCL
V
DDSPD
REV 1.1
09/2007
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT2GT64U8HB0JY
2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Functional Block Diagram
(2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
CS1
CS0
DQS0
DQS0
DM0
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D0
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D8
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5
DM5
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D1
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6
DM6
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D2
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D10
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7
DM7
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D11
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D7
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D6
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D14
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D5
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D13
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D4
BA0-BA2
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
BA0-BA2 : SDRAMs D0-D15
A0-A13 : SDRAMs D0-D15
RAS : SDRAMs D0-D15
CAS : SDRAMs D0-D15
WE : SDRAMs D0-D15
CKE : SDRAMs D0-D7
CKE : SDRAMs D8-D15
ODT : SDRAMs D0-D7
ODT : SDRAMs D8-D15
V
DDSPD
V
DDQ
V
DD
V
REF
V
SS
SPD
D0-D15
D0-D15
D0-D15
D0-D15
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
REV 1.1
09/2007
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
淘e淘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
