NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Based on DDR2-533/667/800 64Mx16 (512MB)/64Mx16 (1GB)/128Mx8 (2GB) SDRAM D-Die
Features
• Performance:
Speed Sort
DIMM CAS Latency
fck – Clock Freqency
tck – Clock Cycle
fDQ – DQ Burst Freqency
PC2-4200
-37B
4
266
3.75
533
PC2-5300
-3C
5
333
3
667
PC2-6400
-AD
6
400
2.5
800
PC2-6400
-AC
5
400
2.5
800
MHz
ns
Mbps
Unit
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 512MB: 64Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx16
DDR2 SDRAM D Die devices.
• 1GB: 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx16
DDR2 SDRAM D Die devices.
• 2GB: 256Mx64 Unbuffered DDR2 SO-DIMM based on 128Mx8
DDR2 SDRAM D Die devices.
• Intended for 266MHz, 333MHz, and 400MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8V ± 0.1V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• Programmable Operation:
- DIMM
Latency: 3, 4, 5 (-37B/-3C/-AC)
- DIMM
Latency: 4, 5, 6 (-AD)
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• 13/10/1 Addressing (512MB)
• 13/10/2 Addressing (1GB)
• 14/10/2 Addressing (2GB)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• 512MB/1GB module’s SDRAMs are 84-ball BGA Package
• 2GB module’s SDRAMs are 60-ball BGA Package
• RoHS compliance
• Halogen free product:
- NT512T64UH4D0FS
- NT1GT64UH8D0FS
- NT2GT64U8HD0BS
Description
NT512T64UH4D0FN, NT512T64UH4D0FS, NT1GT64UH8D0FN, NT1GT64UH8D0FS, NT2GT64U8HD0BN and NT2GT64U8HD0BS are
unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as
one rank (512MB)/two ranks (1GB/2GB) of 64Mx64 (512MB)/128Mx64 (1GB)/256Mx64 (2GB) high-speed memory array.
NT512T64UH4D0FN and NT512T64UH4D0FS use four 64Mx16 84-ball BGA packaged devices; NT1GT64UH8D0FN and
NT1GT64UH8D0FS use eight 64Mx16 84-ball BGA packaged devices; NT2GT64U8HD0BN and NT2GT64U8HD0BS use sixteen 128Mx8
60-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs.
The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SODIMMs provide a
high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 266MHz (333MHz or 400MHz) clock speeds and achieves high-speed data
transfer rates of 533Mbps (667Mbps or 800Mbps). Prior to any access operation, the device
latency and burst/length/operation type
must be programmed into the DIMM by address inputs A0-A12 (512MB/1GB)/A0-A13 (2GB) and I/O inputs BA0, BA1 and BA2 using the
mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are
programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
03/2008
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Ordering Information
Part Number
NT2GT64U8HD0BN – AC
NT2GT64U8HD0BN – AD
NT2GT64U8HD0BN – 3C
Speed
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
256Mx64
Organization
Power
Leads
Note
NT2GT64U8HD0BN – 37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
NT2GT64U8HD0BS – AC
NT2GT64U8HD0BS – AD
NT2GT64U8HD0BS – 3C
NT2GT64U8HD0BS – 37B
NT1GT64UH8D0FN – AC
NT1GT64UH8D0FN – AD
NT1GT64UH8D0FN – 3C
NT1GT64UH8D0FN – 37B
NT1GT64UH8D0FS – AC
NT1GT64UH8D0FS – AD
NT1GT64UH8D0FS – 3C
NT1GT64UH8D0FS – 37B
NT512T64UH4D0FN – AC
NT512T64UH4D0FN – AD
NT512T64UH4D0FN – 3C
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
128Mx64
1.8V
Gold
NT512T64UH4D0FN – 37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
NT512T64UH4D0FS – AC
NT512T64UH4D0FS – AD
NT512T64UH4D0FS – 3C
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5)
DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
64Mx64
NT512T64UH4D0FS – 37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
REV 1.2
03/2008
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Pin Description
CK0, CK1,
,
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
,
A0-A9 A11-A13
A0-A9
A10/AP
BA0, BA1, BA2
ODT0, ODT1
NC
Chip Selects
Row Address Inputs
Column Address Inputs
Column Address Input/Auto-precharge
SDRAM Bank Address Inputs
Active termination control lines
No Connect
DQ0-DQ63
DQS0-DQS7
-
DM0-DM7
V
DD
V
REF
V
DDSPD
V
SS
SCL
SDA
SA0, SA1
Data input/output
Bidirectional data strobes
Differential data strobes
Input Data Masks
Power (1.8V)
Ref. Voltage for SSTL_18 inputs
Serial EEPROM positive power supply
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
CKE0, CKE1
Note: CKE1,
and ODT1 are for 1GB/2GB modules only.
A13 is for 2GB modules only.
REV 1.2
03/2008
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
512MB/1GB/2GB DDR2 SDRAM SODIMM Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
Front
V
REF
V
SS
DQ0
DQ1
V
SS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
Back
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Front
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1/NC
Back
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Front
A1
V
DD
A10/AP
BA0
V
DD
/NC
V
DD
ODT1/NC
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
A0
V
DD
BA1
Pin
151
153
155
157
159
Front
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
V
DD
ODT0
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5
V
SS
161
163
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
A13/NC 165
V
SS
DQ32
DQ33
V
SS
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
CKE1,
and ODT1 are for 1GB/2GB modules only.
A13 is for 2GB modules only.
REV 1.2
03/2008
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Input/Output Functional Description
Symbol
CK0, CK1
,
CKE0, CKE1
,
Type
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Polarity
Positive
Edge
Negative
Edge
Active
High
Active
Low
Active
Low
Active
High
-
Function
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising edge
of their associated clocks.
The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock,
executed by the SDRAM.
Reference voltage for SSTL-18 inputs
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12/A13 define the row address (RA0-RA12/RA13)
when sampled at the rising clock edge. A13 applies on 2GB SODIMM only.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge. In addition to the column address, AP is used to invoke
Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1/BA2 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1/BA2 to control
which bank(s) to precharge. If AP is high all 8 banks will be precharged regardless of the state of
BA0/BA1/BA2. If AP is low, then BA0/BA1/BA2 are used to define which bank to pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Positive
Edge
Active
High
-
-
-
Supply
Data strobe for input and output data
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high. In
Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not
used on x64 modules.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the Serial
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
,
V
REF
,
(SSTL)
Supply
Input
(SSTL)
,
,
define the operation to be
ODT0, ODT1
BA0, BA1, BA2
A0 – A9
A10/AP
A11, A12/A13
(SSTL)
-
DQ0 – DQ63
V
DD
,
V
SS
DQS0 – DQS7
–
(SSTL)
Supply
(SSTL)
Active
High
DM0 – DM7
Input
SA0 – SA1
SDA
SCL
V
DDSPD
REV 1.2
03/2008
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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