M2N25664TUH4B0F / M2N51264TUH8B0F
M2N1G64TU8HB0B
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
200 pin Unbuffered DDR2 SO-DIMM
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 32Mx64 and 64Mx64 Unbuffered DDR2 SO-DIMM based on
32Mx16 Elixir DDR2 SDRAM B-Die devices.
• 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx8 Elixir
DDR2 SDRAM B-Die devices.
• Performance:
PC2-
4200
Speed Sort
DIMM
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
f
DQ
DQ Burst Frequency
37B
4
266
3.75
533
PC2-
5300
3C
5
333
3
667
MHz
ns
MHz
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
Latency: 3, 4, 5
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (256MB)
13/10/2 Addressing (512MB)
14/10/2 Addressing (1GB)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 84-ball BGA Package (256MB&512MB)
• SDRAMs in 60-ball BGA Package (1GB)
• RoHS compliance
Based on Elixir DDR2-533/667 32Mx16/64Mx8 SDRAM B-Die
Unit
• Intended for 266MHz and 333MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8V ± 0.1V
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
Description
M2N25664TUH4B0F, M2N51264TUH8B0F, and M2N1G64TU8HB0B are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous
DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 32x64 (256MB), two ranks of 64x64 (512MB), and
two ranks of 128x64(1GB) high-speed memory array. Modules use four 32Mx16 (256MB) and eight 32Mx16 (512MB) 84-ball BGA
packaged devices. Modules use sixteen 64Mx8 (1GB) 60-ball BGA packaged devices. These DIMMs are manufactured using raw cards
developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 266MHz/333MHz clock speeds and achieves high-speed data transfer rates of
533MHz/667MHz. Prior to any access operation, the device
latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
07/2006
REV 1.0
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M2N25664TUH4B0F / M2N51264TUH8B0F
M2N1G64TU8HB0B
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Ordering Information
Part Number
M2N25664TUH4B0F–3C
Speed
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
32Mx64
M2N25664TUH4B0F–37B
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
Organization
Power
Leads
Note
M2N51264TUH8B0F–3C
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
64Mx64
1.8V
Gold
M2N51264TUH8B0F–37B
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
M2N1G64TU8HB0B -3C
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
128Mx64
M2N1G64TU8HB0B -37B
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
07/2006
REV 1.0
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M2N25664TUH4B0F / M2N51264TUH8B0F
M2N1G64TU8HB0B
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Pin Description
CK0, CK1,
,
CKE0, CKE1
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
,
A0-A13
A0-A9
A10/AP
BA0, BA1
ODT0, ODT1
NC
Chip Selects
Row Address Inputs
Column Address Inputs
Column Address Input/Auto-precharge
SDRAM Bank Address Inputs
Active termination control lines
No Connect
DQ0-DQ63
DQS0-DQS7
-
DM0-DM7
V
DD
V
REF
V
DDSPD
V
SS
SCL
SDA
SA0, SA1
Data input/output
Bidirectional data strobes
Differential data strobes
Input Data Masks
Power (1.8V)
Ref. Voltage for SSTL_18 inputs
Serial EEPROM positive power supply
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
Front
V
REF
V
SS
DQ0
DQ1
V
SS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
Back
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Front
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
NC
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
Back
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
V
DD
Front
A1
V
DD
A10/AP
BA0
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
DQS5
V
SS
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Back
A0
V
DD
BA1
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
Front
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
Back
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
07/2006
REV 1.0
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M2N25664TUH4B0F / M2N51264TUH8B0F
M2N1G64TU8HB0B
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Input/Output Functional Description
Symbol
CK0, CK1
,
CKE0, CKE1
Type
(SSTL)
(SSTL)
(SSTL)
Polarity
Function
The positive line of the differential pair of system clock inputs which drives the input to the
Positive
on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising
Edge
edge of their associated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to the
Edge on-DIMM PLL.
Active
High
Active
Low
Active
Low
Active
High
-
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP
is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If
AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If
AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Data strobe for input and output data
Positive
Edge
Active
High
-
-
-
Supply
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if it
is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
,
(SSTL)
,
V
REF
,
(SSTL)
Supply
Input
(SSTL)
,
,
define the operation
ODT0, ODT1
BA0, BA1
A0 - A9
A10/AP
A11, A13
(SSTL)
-
DQ0 – DQ63
V
DD
,
V
SS
DQS0 – DQS7
–
(SSTL)
Supply
(SSTL)
Active
High
DM0 – DM7
Input
SA0 – SA2
SDA
SCL
V
DDSPD
07/2006
REV 1.0
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M2N25664TUH4B0F / M2N51264TUH8B0F
M2N1G64TU8HB0B
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Functional Block Diagram
(256MB
–
1 Rank, 32Mx16 DDR2 SDRAMs)
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07/2006
REV 1.0
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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