Product Specification
PE99151 DIE
Product Description
The PE99151 is a radiation tolerant point-of-load buck
regulator delivering high efficiency at V
IN
= 5V and output
currents up to 2A continuous. This single-chip solution is
perfect for Hi-Rel applications and delivers peak
efficiency exceeding 93%. A minimal external component
count and high switching frequency enables >10 W/in
2
standard PCB designs while high efficiency minimizes
thermal concerns. All power switching devices are
integrated on-chip.
Fabricated in Peregrine’s patented UltraCMOS
®
technology, the PE99151 offers excellent power
efficiency and intrinsic radiation tolerance.
Hi-Rel 2A DC-DC Converter
Radiation Tolerant UltraCMOS
®
Monolithic Point-of-Load Synchronous
Buck Regulator with Integrated Switches
Features
Up to 2A continuous
Output voltage range from 1.0–3.6V
by external select resistors
Input voltage range 4.6–6.0V
Current mode control, pulse-by-pulse
current limit, current sharing enabled
and (N+K) redundancy compatible
shutdown mode
SYNC function, 100 kHz–5 MHz lock
range with selectable 500 kHz /1 MHz
free running frequency
Shutdown pin, Power Good output pin
for supply sequencing
Better than 1% typical initial accuracy
(25°C)
Control inputs compatible with TTL,
LVTTL, LVCMOS (2.5V and 3.3V)
and 5V CMOS
Table 1. Radiation Performance
TID
SEL
SEB
SET
SEFI
SEGR
100 kRad(Si)
> 90 MeV•cm
2
/mg
> 90 MeV•cm
2
/mg
> 90 MeV•cm
2
/mg
> 90 MeV•cm
2
/mg
> 90 MeV•cm
2
/mg
SEL, SEB, SEGR, SEU, SEFI: None observed, Au/60 degrees
SET: No events exceeding 30 mV transient observed @ Au,
LET=90, 60 degrees and normal incidence
Figure 1. Typical Application Diagram
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PE99151 DIE
Product Specification
Table 2. Electrical Specifications
1
Temp (T
A
) = –55 °C to +125 °C, V
IN
= 4.6–6.0V, V
OUT
= 1.0–3.6V, unless otherwise noted
Parameter
Synchronous Frequency Range,
Fsw_range
Maximum Cycle-Averaged RMS
Output Current,
Imax
Supply Current (Shutdown),
IDDSD
Supply Current (No-load, 1 MHz
async),
IDD0
High Side On Resistance,
Ron,hss
Low Side On Resistance,
Ron,lss
Output Voltage
Reference Voltage Accuracy,
Vref
2
Reference Voltage Line Regulation,
Kvi (steady state)
2
Reference Voltage Load Regulation,
Kvo (steady state)
2
Internal Oscillator and SYNC Capture
Oscillator Frequency,
FOSC_FREQ
Internal Oscillator Duty Cycle,
FOSC_DC
SYNC Lock Capture Frequency,
Sync_lock
External Sync Duty Cycle,
SYNC_DC
Current Limiting and Current Mode Control Loop
Internal Current Limit Max,
ILIMXINT
2
Externally Set Max Current Limit
Accuracy,
ILIMXEXT
2
Max voltage across Rset,
VMAXRSET
I
out
/I
rset,
G
Iref 2
ICOMP cap,
CICOMP
2
Current compensation gain, ICOMP
gain,
G
ICOMP 2
2.3
I
OUT
set for 50% rated current
V
OUT
= 1.0V, ISET = 3.0V, ICOMP = 0V, RSEL pin shorted to ground,
not min-on-time limited
V
OUT
= 1.0V, RSET = 130Ω, ISET = 3.0V, ICOMP = 0V, RSEL = V
IN
,
not min-on-time limited
2
2
1.3
300
3
3
1.5
378
110
3
4
4
4
1.75
450
A
%
V
A/A
pF
A/V
SYNC = GND
SYNC = Open or V
IN
320
0.71
46
40
40
60
530
1
700
1.42
54
kHz
MHz
%
kHz
%
V
IN
= 5.0V, I
OUT
= Imax/2, –40≤ T
A
≤
+85 °C, Fsw = 100 kHz–1 MHz
V
IN
= 5.0V, I
OUT
= Imax/2, –55≤ T
A
≤
+125 °C, Fsw = 100 kHz–1 MHz
4.6V
≤
V
IN
≤
6.0V, I
OUT
= 1A, V
OUT
= 2.5V, Fsw = 1 MHz
V
IN
= 5.0V, 500 mA
≤
I
OUT
≤
1A, V
OUT
= 2.5V, Fsw = 1 MHz
–1.0
–1.5
–0.2
–0.25
0
0
0
0
1.0
1.5
0.2
0.25
%
%
%
Test current = 100 mA
Test current = 100 mA
97
113
SDb = GND, V
IN
= 5.5V
SDb = GND, V
IN
= 6.0V
Condition
Min
0.1
2
1.8
3.1
3.2
5.5
17.5
160
190
mA
mΩ
mΩ
Typ
Max
5
Unit
MHz
A
mA
Notes: 1. Wafer level screening is performed at +25 °C and +85 °C only. However, performance is guaranteed over the full operating temperature range based on a
population of parts that were packaged and characterized at –55 °C and +125 °C.
2. Parameter not tested at wafer level due to high current limitations of test setup.
©2012–2015 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
Document No. DOC-50370-6
│
UltraCMOS
®
Power Management Solutions
PE99151 DIE
Product Specification
Table 2. Electrical Specifications* (Continued)
Temp (T
A
) = –55 °C to +125 °C, V
IN
= 4.6–6.0V, V
OUT
= 1.0–3.6V, unless otherwise noted
Parameter
PGOOD
EAINM_UP_THRESH entering PGOOD window
(% of Vref)
EAINM_LO_THRESH exiting PGOOD window
(% of Vref)
EAINM_UP (% of Vref)
EAINM_LO
V_PGOOD = 0.4V
V_PGOOD = V
IN
3.5
103
83
110
89
2
1.67
8
9
64
22.5
mA
uA
SYNCOb
cycles
118
98
%
%
%
Condition
Min
Typ
Max
Unit
PGOOD Threshold
PGOOD hysteresis
PGOOD low sink current,
PGOOD I_OL
PGOOD high leakage current,
PGOOD I_OH
PGOOD Deglitch Time
Error Amp
EAINM leakage
EAINP leakage
EAOUT Source Current
EAOUT Sink Current
Error Amplifier Transconductance
Error Amplifier Output Resistance
EA Input offset
Undervoltage Lockout
Under-voltage Lockout
Under-voltage Lockout Hysteresis
Soft Start
SS pin pull-up Resistance
Internal
SSCAP
Vref Track,
V_SScap – Vref_ext
DC Characteristics
SDb turn-on threshold
SYNCOb low sink current,
SYNCOb I_OL
SYNCOb high leakage current,
SYNCOb I_OH
SYNC
HSS Leakage
LSS Leakage
Measured at 1V input
Measured at 1V input
Measured at 1V input
Measured at 1V input
EAOUT = 1.5V, DC
–490
100
0.4
3.5
1 MHz internal
–6
–345
200
1.25
6.5
4
0.2
0.2
–220
295
2.2
9.5
6
uA
uA
uA
uA
mS
MΩ
mV
V
IN
Rising
V
IN
Falling
3.5
3.4
4.2
3.8
400
4.59
4.1
V
V
mV
VSSCAP = 0V
1.2
16
MΩ
pF
170
mV
VSSCAP = 0.5V
–170
0
V
IH
V
IL
V_SYNCOb = 0.4
V_SYNCOb = V
IN
V
IH
V
IL
V
OUT
= SDb = 0V
V
OUT
= V
IN
, SDb = 0V
2
1.45
3.5
8
9
2
1.25
–0.09
–0.001
0.09
0.7
22.5
V
V
mA
µA
V
V
mA
mA
Note: * Wafer level screening is performed at +25 °C and +85 °C only. However, performance is guaranteed over the full operating temperature range based on
a population of parts that were packaged and characterized at –55 °C and +125 °C.
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Page 3 of 15
PE99151 DIE
Product Specification
Figure 2. Pin Layout (Top View)*
Note: * All pin locations originate from the die center and refer to the center of the pin.
Table 3. Pin Coordinates and Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin
Name
GND
SW
SW
GND
SW
SW
GND
SW
SW
GND
GND
ICOMP
ISET
EAOUT
X
1385.9
1366.9
1366.9
1365.9
1366.9
1366.9
1366.9
1366.9
1366.9
1385.9
Y
1433.4
1179.65
810.35
500
189.65
–189.65
–500
–810.35
Ground
Switch
Switch
Ground
Switch
Switch
Ground
Switch
20
21
22
23
24
TCSEL0
TCSEL1
GND
CCSEL
EAINM
–1343.9
–1343.9
–1343.9
–1343.9
–1343.9
148.5
297.2
500
696.1
869.7
Description
Pin
No.
15
16
17
18
19
Pin Name
VREFSEL0
GND
VREFSEL1
VREFSEL2
VREFSEL3
X
–1343.9
–1343.9
–1343.9
–1343.9
–1343.9
Y
–696.1
–500
–297.3
–148.7
–0.1
Description
Bandgap Reference
Voltage Fine Adjust (0)
Ground
Bandgap Reference
Voltage Fine Adjust (1)
Bandgap Reference
Voltage Fine Adjust (2)
Bandgap Reference
Voltage Fine Adjust (3)
Bandgap Reference Voltage
Fine Adjust (0)
Bandgap Reference Voltage
Fine Adjust (0)
Ground
Course trim code
Error Amplifier (–) Input,
Loop to VREF
–1179.65 Switch
–1433.4
Ground
–1343.9 –1437.25 Switch
–1343.9
–1343.9
–1343.9
–1266.9
–1068.3
–869.7
Variable Current Compensa-
tion/Resistor to VOUT
Current Set-Point Input/Loop to
EAOUT
Error Amplifier Output/Loop
ISET
©2012–2015 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. DOC-50370-6
│
UltraCMOS
®
Power Management Solutions
PE99151 DIE
Product Specification
Table 3. Pin Coordinates and Descriptions
(continued)
Pin
No.
25
Pin Name
EAINP
X
–1343.9
Y
1068.3
Description
Error Amplifier (+) Input,
Load Feedback
1.000V Reference output,
Loop to AAINP. Additional
Low Pass Filtering May be
Necessary
Ground
Bandgap ground
Resistor to Set Reference
Current
Resistor to Set Reference
Current
Loop-Through Comple-
ment Output
Loop-Through Comple-
ment Output
Power Good Flag Output
Shutdown (L)/enable input
Reference Resistor
Selection
Ground
Ground
Input Power Supply
Input Power Supply
Input Power Supply
Table 4. Operating Ranges
Symbol
V
IN
T
A
Parameter/Condition
Power supply voltage
Operating temperature range
(ambient)
Min
4.6
–55
Max
6.0
+125
Unit
V
°C
26
VREF
–1343.9
1266.9
Table 5. Absolute Maximum Ratings
Symbol
V
IN
T
j
T
ST
I
I
I
O
I
P
Parameter/Condition
Power supply voltage
Operating temperature range
(junction)
Storage temperature range
DC into any signal input
DC into any signal output
DC into any
single
power pin
Min
–0.5
–55
–65
–10
–50
–2
Max
6.5
+145
+150
10
50
2
Unit
V
o
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
AGND
RSET
SScap
SYNCOb
SYNC
PGOOD
SDb
RSEL_SDAT
TEST
SCLK
V
IN
V
IN
V
IN
–1343.9
–1142.8
–1142.8
–944.2
–944.2
–745.6
–745.6
–547
–547
–348.4
–348.4
602.5
1102.5
602.5
1437.25
1283.2
–1283.2
1283.2
–1283.2
1283.2
–1283.2
1283.2
–1283.2
1283.2
–1283.2
1000
0
–1000
C
C
o
mA
mA
A
Exceeding absolute maximum ratings may cause
permanent damage. Operation between maximum
operating range and absolute maximum for
extended periods may reduce reliability.
Table 6. Electrostatic Discharge (ESD) Ratings
Model
HBM*
Parameter/Condition
V
ESD
All pins
Min
Max
1000
Unit
V
Note: * Human Body Model ESD Voltage (HBM, MIL_STD 883 Method 3015.7).
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Immunity
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
ELDRS
The UltraCMOS process does not exhibit enhanced
low-dose-rate sensitivity (ELDRS) since bipolar
minority carrier elements are not used.
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