Product Specification
PE97240
Product Description
Peregrine’s PE97240 is a radiation tolerant high-
performance Integer-N PLL capable of frequency
synthesis up to 5 GHz. The device is designed for
commercial space applications and optimized for
superior phase noise performance.
The PE97240 features a selectable prescaler
modulus of 5/6 or 10/11, counters and a phase
comparator as shown in
Figure 1.
Counter values are
programmable through either a serial interface or
directly hard-wired.
The PE97240 is available in a 44-lead CQFP and is
manufactured on Peregrine’s UltraCMOS
®
process, a
patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering excellent
RF performance and intrinsic radiation tolerance.
Radiation Tolerant UltraCMOS
®
Integer-N Frequency Synthesizer
for Low Phase Noise Applications
Features
Frequency range
5 GHz in 10/11 prescaler modulus
4 GHz in 5/6 prescaler modulus
Phase noise floor figure of merit:
–230 dBc/Hz
Low power: 75 mA @ 2.7V
Serial or direct mode access
Packaged in a 44-lead CQFP
100 kRad(Si) total dose
Figure 1. Functional Diagram
PE97240
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PE97240
Product Specification
Figure 2. Pin Configurations (Top View)
Figure 3. Package Type
44-lead CQFP
Table 1. Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Name
V
DD
R4
R5
A3
GND
M3
M2
M1
M0
V
DD
GND
M8
M7
SCLK
M6
15
SDATA
M5
S_WR
M4
Interface Mode
Both
Direct
Direct
Direct
Both
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
Serial
Direct
Serial
Direct
Serial
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Note 1
Type
Note 1
Input
Input
Input
Description
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
R counter bit4
R counter bit5
A counter bit3
Ground
M counter bit3
M counter bit2
M counter bit1
M counter bit0
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Ground
M counter bit8
M counter bit7
Serial clock input. SDATA is clocked serially into the 21-bit primary register (E_WR “low”)
or the 8-bit enhancement register (E_WR “high”) on the rising edge of SCLK.
M counter bit6
Binary serial data input. Input data entered MSB first.
M counter bit5
Serial load enable input. While S_WR is “low”, SDATA can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
M counter bit4
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®
RFIC Solutions
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16
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PE97240
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
17
18
19
Pin Name
Direct
A0
A1
E_WR
A2
V
DD
Pre_en
Pre_5/6_Sel
V
DD
F
IN
Interface Mode
Direct
Direct
Direct
Serial
Direct
Both
Direct
Direct
Both
Both
Type
Input
Input
Input
Input
Input
Note 1
Input
Input
Note 1
Input
Description
Select “High” enables Direct Mode. Select “Low” enables Serial Mode.
A counter bit0
A counter bit1
Enhancement register write enable. While E_WR is “high”, SDATA can be serially
clocked into the enhancement register on the rising edge of SCLK.
A counter bit2
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Prescaler enable, active “low”. When “high”, F
IN
bypasses the prescaler.
5/6 modulus select, active “High.” When “Low,” 10/11 modulus selected.
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Prescaler complementary input. A 22 pF bypass capacitor should be placed as close
as possible to this pin and be connected in series with a 50Ω resistor to ground.
Prescaler input from the VCO, 5.0 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and be connected in shunt to a
50Ω resistor to ground.
Ground
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Logical “NAND” of PD_D
and PD_U
terminated
through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Lock detect and open drain logical inversion of C
EXT
. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Power supply input. Input may range from 2.6V to 2.8V. Bypassing recommended.
PD_D
is pulse down when f
p
leads f
c
PD_U is pulse down when f
c
leads f
p
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Ground
Input
Note 1
Input
Input
Input
Input
Input
Reference frequency input
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
R counter bit0
R counter bit1
R counter bit2
R counter bit3
Ground
20
21
22
23
24
25
26
27
28
F
IN
GND
D
OUT
Both
Both
Serial
Input
29
C
EXT
Both
Output
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Notes:
LD
V
DD
PD_D
PD_U
V
DD
V
DD
GND
F
R
V
DD
ENH
R0
R1
R2
R3
GND
Both
Both
Both
Both
Both
Both
Both
Both
Both
Serial
Direct
Direct
Direct
Direct
Both
Output
Note 1
Output
Output
Note 1
Note 1
1. V
DD
pins 1, 10, 21, 24, 31, 34, 35 and 38 are connected by diodes and must be supplied with the same positive voltage level.
2. All digital input pins have 70 kΩ pull-down resistors to ground.
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PE97240
Product Specification
Table 2. Operating Ratings
Parameter/Condition
Supply voltage
Operating ambient
temperature range
Symbol
V
DD
T
A
Min
2.6
–40
Max
2.8
+85
Unit
V
C
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Immunity
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
ELDRS
UltraCMOS devices do not include bipolar minority
carrier elements, and therefore do not exhibit
enhanced low dose rate sensitivity.
Table 4. Single Event Effects
1
SEE Mode
SEL
300
V
SEFI
SEU
SET
Notes:
Table 3. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Voltage on any input
DC into any input
DC into any output
RF input power, CW
50 MHz–5 GHz
Thermal resistance
Junction temperature
Storage temperature range
ESD voltage HBM
1
All pins except pin 28
ESD voltage HBM
On pin 28
1,2
Symbol
V
DD
V
I
I
I
I
O
P
MAX_CW
T
JC
T
J
T
ST
Min
–0.3
–0.3
–10
–10
Max
3.3
V
DD
+ 0.3
+10
+10
10
33.4
+125
Unit
V
V
mA
mA
dBm
°C/W
°C
°C
V
–65
+150
1000
Effective Linear Energy Transfer (LET)
2
86 MeVcm
2
/mg
86 MeVcm
2
/mg
86 MeVcm
2
/mg
30 MeVcm
2
/mg
3
V
ESD_HBM
Notes: 1. Human Body Model (MIL-STD-883 Method 3015).
2. Pin 28 is not used in normal operation.
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
1. Testing performed using serial programming mode.
2. SEE testing was conducted with Au, Ho, Xe, Kr, Cu ion species at 0°
incidence.
3. Minor transients (phase errors) observed resulting in self-recovering
operation without intervention.
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
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Document No. DOC-15214-7
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UltraCMOS
®
RFIC Solutions
PE97240
Product Specification
Table 5. DC Characteristics @ V
DD
= 2.7V, –40 °C < T
A
< +85 °C, unless otherwise specified
Symbol
Parameter
Condition
Prescaler disabled,
f
C
= 50 MHz, F
IN
= 500 MHz
V
DD
= 2.6–2.8V
I
DD
Operational supply current
5/6 prescaler,
f
C
= 50 MHz, F
IN
= 3 GHz
V
DD
= 2.6–2.8V
10/11 prescaler,
f
C
= 50 MHz, F
IN
= 3 GHz
V
DD
= 2.6–2.8V
Digital Inputs: All except F
R
, F
IN
, F
IN
V
IH
V
IL
I
IH
I
IL
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.6–2.8V
V
DD
= 2.6–2.8V
V
IH
= V
DD
= 2.8V
V
IL
= 0, V
DD
= 2.8V
–10
0.7 x V
DD
0.3 x V
DD
70
V
V
μA
μA
Min
Typ
34
Max
50
Unit
mA
72
105
mA
74
110
mA
Reference Divider input: F
R
I
IHR
I
ILR
High level input current
Low level input current
V
IH
= V
DD
= 2.8V
V
IL
= 0, V
DD
= 2.8V
–300
300
μA
μA
Counter and phase detector outputs: PD_D, PD_U
V
OLD
V
OHD
Output voltage LOW
Output voltage HIGH
I
out
= 6 mA
I
out
= –3 mA
V
DD
– 0.4
0.4
V
V
Lock detect outputs: C
EXT
, LD
V
OLC
V
OHC
V
OLLD
Output voltage LOW, C
EXT
Output voltage HIGH, C
EXT
Output voltage LOW, LD
I
out
= 100
μA
I
out
= –100
μA
I
out
= 1 mA
V
DD
– 0.4
0.4
0.4
V
V
V
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