NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
184pin One Bank Unbuffered DDR SDRAM MODULE
Based on DDR266/200 16Mx8 SDRAM
Features
• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
• 16Mx64 Double Data Rate (DDR) SDRAM DIMM
(16M X 8 SDRA MS)
• Performance :
Speed Sort
DIMM
CAS
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
PC1600
- 8B
2
100
10
PC2100
- 75B
- 7K
2.5
133
7.5
2
133
7.5
MHz
ns
Unit
• Data is read or written on both clock edges
• DRAM D
LL
aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
f
DQ
DQ Burst Frequency
200
266
266
MHz
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= 2.5Volt ±?0.2, V
DD
= 2.5Volt ± 0.2
• Single Pulsed
RAS
interface
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
Description
NT128D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 16Mx64 module is a single-bank DIMM that uses eight 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number
NT128D64S88A0G-7K
Speed
143MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
NT128D64S88A0G –75B
133MHz (7.5ns @ CL= 2.5 )
100MHz (10ns @ CL = 2 )
NT128D64S88A0G –8B
125MHz (8ns @ CL = 2.5 )
100MHz (10ns @ CL = 2 )
PC1600
PC2100
16Mx64
Gold
2.5V
PC2100
Organization
Leads
Power
REV1.0
/
June 2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
Pin Description
CK0, CK1, CK2
CK0
,
CK1
,
CK2
CKE0
RAS
CAS
WE
S0
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
(Not used when V
DD
=V
DDQ)
DQ0-DQ63
DQS0-DQS7,
DQS9-DQS16
VDD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bidirectional data strobes
Power (2.5V)
Supply voltage for DQs(2.5V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply(2.5V)
A0-A9, A11
A10/AP
BA0, BA1
V
REF
V
DDID
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Front
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
CK1
V
SS
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Back
V
SS
DQ4
DQ5
V
DDQ
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
NC
V
DDQ
NC
DQ20
NC
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
NC
A0
NC
V
SS
NC
BA1
KEY
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Back
V
SS
A6
DQ28
DQ29
V
DDQ
DQS12
A3
DQ30
V
SS
DQ31
NC
NC
V
DDQ
CK0
CK0
V
SS
NC
A10
NC
V
DDQ
NC
KEY
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
V
DDQ
WE
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ41
CAS
DQ45
V
DDQ
S0
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
CK2
CK2
NC
DQS14
V
SS
DQ46
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
31
DQ19
123
DQ23
61
DQ40
153
Note:
All pin assignments are consistent for all 8-byte unbuffered versions.
REV1.0
/
June 2001
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
Input/Output Functional Description
Symbol
CK0 , CK1, CK2
Type
(SSTL)
Polarity
Function
The positive line of the differential pair of system clock inputs which drives the input to the
Positive
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
Edge
edge of their associated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to the
Edge on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
Active
High deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
Active
decoder when high. When the command decoder is disabled, new commands are ignored
Low
but previous operations continue.
Active When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
Low
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
CK0
,
CK1
,
CK2
(SSTL)
CKE0
(SSTL)
S0
(SSTL)
RAS
,
CAS
,
WE
(SSTL)
Supply
Supply
(SSTL)
V
REF
V
DDQ
BA0, BA1
A0 - A9
A10/AP
A11
(SSTL)
-
DQ0 - DQ63,
DQS0 - DQS7
DQS9 - DQS16
V
DD
, V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
(SSTL)
(SSTL)
Supply
-
Active Data strobes: Output with read data, input with write data. Edge aligned with read data,
High centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
-
-
-
Supply
REV1.0
/
June 2001
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
Functional Block Diagram
( 1 Bank, 16Mx8 DDR SDRAMs )
S0
DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S0
BA0-BA1
A0-A11
RAS
CAS
CKE0
WE
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS4
DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CK0
120 ohm
CK0
CK1
120 ohm
CK1
CK2
120 ohm
CK2
VDDQ
VDD
VREF
VSS
VDDID
D0
D0
D0
D0
-
-
-
-
D7
D7
D7
D7
SDRAM x 3
SDRAM x 3
SDRAM x 2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D0
D4
D1
D5
D2
D6
D3
D7
CS : SDRAMs D0 -D7
BA0 - BA1 : SDRAMs D0 -D7
A0 - A11 : SDRAMs D0 -D7
RAS : SDRAMs D0 -D7
CAS : SDRAMs D0 -D7
CKE0 : SDRAMs D0 -D7
WE : SDRAMs D0 -D7
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
Notes :
1.
2.
3.
4.
Strap: see Note 4
DQ-to-I/O wring may be changed within a byte.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22 Ohms.
VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
REV1.0
/
June 2001
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect --
Part 1 of 2
16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Description
Number of Serial PD Bytes Written during
Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=2.5
DDR SDRAM Device Access Time from
Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
DDR SDRAM Device Attributes:
Burst Length Supported
DDR SDRAM Device Attributes: Number of
Device Banks
DDR SDRAM Device Attributes: CAS
Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at
CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time(t
RP
)
Minimum Row Active to Row Active delay
(t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before
Clock
Address and Command Hold Time After
Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum Data
Initial
20ns
15ns
20ns
45ns
2/2.5
7ns
0.75ns
SPD Entry Value
DDR266A DDR266B DDR200
-7K
-75B
-8B
128
256
DDR SDRAM
12
10
1
X64
X64
SSTL 2.5V
7.5ns
0.75ns
Non-Parity
SR/1x(15.625us)
X8
N/A
1 Clock
2,4,8
4
2/2.5
0
1
Differential Clock
+/-0.2V Voltage Tolerance
7.5ns
10ns
10ns
0.75ns
0.75ns
N/A
N/A
20ns
15ns
20ns
45ns
128MB
0.9ns
0.9ns
0.5ns
0.5ns
0.9ns
0.9ns
0.5ns
0.5ns
Undefined
Initial
Initial
00
6C
1.1ns
1.1ns
0.6ns
0.6ns
90
90
50
50
20ns
15ns
20ns
50ns
50
3C
50
2D
0.8ns
75
75
2/2.5
0C
8ns
0.8ns
70
75
Serial PD Data Entry (Hexadecimal) Note
DDR266A DDR266B DDR200
-7K
-75
-8B
80
08
07
0C
0A
01
40
00
04
75
75
00
80
08
00
01
0E
04
0C
01
02
20
00
A0
75
00
00
50
3C
50
2D
20
90
90
50
50
00
00
9C
00
22
B0
B0
60
60
50
3C
50
32
A0
80
0C
80
80
0
1
2
3
4
5
6.
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
REV1.0
/
June 2001
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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