NT4GTT72U4PB1UN-3C
4GB: 512Mx72
240pin DDR2 SDRAM Fully Buffered DIMM
Based on 512Mx4 (2x256Mx4 DDP) DDR2 SDRAM - B die
Features
• 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 512Mx4
DDR2 SDRAM (NT5TU512T4BU-3C).
• JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line
Memory Module.
• Performance:
FBDIMM
Speed Sort
DRAM
DIMM
Latency
Channel Clock
DRAM Clock
PC2-5300
-3C
DDR2-667
5
166
333
t
CK
MHz
MHz
Unit
compliant.
• Support SMBus protocol interface for access to the AMB
configuration registers.
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• MBIST & IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Serial Presence Detect (SPD)
• Gold contacts
• RoHS Compliance
• SDRAM in 71-ball BGA Dual Die Package
• Intended for 333MHz applications.
• Inputs and outputs are SSTL-18 compatible.
• V
DD
= 1.8Volt ± 0.1, V
DDQ
= 1.8Volt ± 0.1.
• Host Interface and AMB component industry standard
Description
NT4GTT72U4PB1UN-3C is Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module
(DIMM) with
INTEL designed Heat Spreader,
organized as two ranks 512Mx72 high-speed memory array. The module uses eighteen
512Mx4 (2Gb) DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as
reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM
DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 333MHz clock speeds and achieves high-speed data transfer rates of up to
667 MHz. Prior to any access operation, the device
latency and burst/length/operation type must be programmed into the DIMM by
address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle.
REV 1.1
9/2008
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT4GTT72U4PB1UN-3C
4GB: 512Mx72
Ordering Information
Part Number
NT4GTT72U4PB1UN-3C
AMB
Intel D1
333MHz
(3ns @ CL = 5)
Speed
DDR2-667
PC2-5300
Organization
512Mx72
Leads
Gold
Note
INTEL Heat
Spreader
REV 1.1
9/2008
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT4GTT72U4PB1UN-3C
4GB: 512Mx72
DIMM Connector Pin Description
Pin Name
SCK
PN0-PN13
-
PS0-PS9
-
SN0-SN13
-
SS0-SS9
-
SCL
SDA
SA0-SA2
VID0-VID1
Pin Description
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address Inputs, also used to select the DIMM number in the AMB
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID0 is V
DD
value: OPEN=1.8V, GND=1.5V; VID1 is V
CC
value: OPEN=1.5V, GND=1.2V
AMB reset signal
RFU
V
CC
V
DD
V
TT
V
DDSPD
V
SS
Reserved for Future Use
AMB Core Power and AMB Channel Interface Power (1.5V)
DRAM Power and AMB DRAM I/O Power (1.8V)
DRAM Address/Command/Clock Termination Power (V
DD
/2)
SPD Power (3.3V)
Ground
It provides an external connection on 512MB/1GB for testing the margin of Vref which is
produced by a voltage divider on the module. It is not intended to be used in normal
system operation and must not be connected (DNU) in a system. This test pin may have
other features on future card designs and if it does, will be included in this specification at
that time.
DNU/M_TEST
Note:
1.
2.
System Clock Signals SCK and SCK switch at one half the DRAM CK/
frequency
Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
REV 1.1
9/2008
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT4GTT72U4PB1UN-3C
4GB: 512Mx72
DDR2 240-pin FBDIMM Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
V
SS
PN13
V
SS
PN5
V
SS
PN4
V
SS
PN3
V
SS
PN2
69
70
71
72
73
74
75
76
77
78
79
80
81
V
SS
V
SS
PS3
V
SS
PS2
V
SS
PS1
V
SS
PN1
V
SS
RFU**
RFU**
V
SS
PN0
Front Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID1
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
V
SS
KEY
V
SS
PS0
V
SS
PN11
V
SS
PN10
V
SS
PN9
V
SS
PN8
V
SS
PN7
V
SS
PN6
Front Side
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
PN12
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
RFU**
RFU**
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
SA2
SDA
SCL
V
SS
PS8
V
SS
PS7
V
SS
PS6
V
SS
PS5
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
PS9
Front Side
PS4
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
SN13
V
SS
SN5
V
SS
SN4
V
SS
SN3
V
SS
SN2
189
190
191
192
193
194
195
196
197
198
199
200
201
V
SS
V
SS
SS3
V
SS
SS2
V
SS
SS1
V
SS
SN1
Back Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID0
DNU/M_TEST
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Back Side
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
SN12
V
SS
SN6
V
SS
SN7
V
SS
SN8
V
SS
SN9
V
SS
SN10
V
SS
SN11
V
SS
KEY
V
SS
SS0
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back Side
SS4
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
SS9
V
SS
SS5
V
SS
SS6
V
SS
SS7
V
SS
SS8
V
SS
RFU**
RFU**
V
SS
SCK
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
V
DDSPD
SA0
SA1
V
SS
RFU**
RFU**
V
SS
SN0
Note:
RFU = Reserved Future Use
* These pin positions are reserved for forwarded clocks to be used in future module implementation
** These pin positions are reserved for future architecture flexibility
The following signals are CRC bits and thus appear out of the normal sequence: PN12/
, SN12/
PS9/
, SS9/
, PN13/
, SN13/
,
REV 1.1
9/2008
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT4GTT72U4PB1UN-3C
4GB: 512Mx72
Functional Block Diagram
(4GB, 2Rank, 512Mx4 DDR2 SDRAMs [256Mx4 dual die])
Vss
S1
S0
DQS 0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
S1
S0
DQS4
DQS4
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6
DQS DQS CS
DQ48
DQ49
DQ50
DQ51
DQS2
DQS2
DQS DQS CS
DQ16
DQ17
DQ18
DQ19
S1
S0
I/ O 0
I/ O 1
I/ O 2
I/O 3
D8
DM
DQS DQS
I/ O 0
I/ O 1
I/ O 2
I/O 3
CS
DM
DQ20
DQ21
DQ22
CB7
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
D3
DM
DQS DQS
I/ O 0
I/ O 1
I/ O 2
I/O 3
D21
CS
DM
DQ52
DQ53
DQ54
DQ55
DQS9
DQS9
DQS DQS CS
I/O 0
I/O 1
D0
I/O 2
I/O 3
DM
DQS DQS CS DM
I/O 0
I/O 1
D18
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10
DQS DQS CS
I/O 0
I/O 1
D1
I/O 2
I/O 3
DM
DQS DQS CS DM
I/O 0
I/O 1
D19
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
DQS14
DQS14
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15
DQS DQS CS
I/O 0
I/O 1
I/O 2
I/O 3
D12
DM
DQS DQS
I/O
I/O
I/O
I/O
0
1
2
3
D30
CS
DM
DQS DQS CS DM
I/O 0
I/O 1
D9
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS CS DM
D27
DQS DQS CS
I/O 0
I/O 1
D10
I/O 2
I/O 3
DM
DQS DQS CS DM
I/O 0
I/O 1
D28
I/O 2
I/O 3
DQS DQS CS
I/O 0
I/O 1
I/O 2
I /O 3
D2
DM
DQS DQS CS
I/O 0
I/O 1
I/O 2
I /O 3
D20
DM
DQS DQS CS
I/O 0
I/O 1
I/O 2
I/O 3
D11
DM
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D29
CS
DM
DQS11
DQS11
DQS DQS CS
I/O 0
I/O 1
I/O 2
I/O 3
D17
DM
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D35
CS DM
D26
DQS4
DQS4
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS CS
D4
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS CS
D22
DM
DQS14
DQS14
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15
DQS DQS CS
I/O 0
I/O 1
D13
I/O 2
I/O 3
DM
DQS DQS CS
I/O 0
I/O 1
D31
I/O 2
I/O 3
DM
DQS DQS CS
I/ O 0
I/ O 1
D5
I/ O 2
I/O 3
DM
DQS DQS CS
I/ O 0
I/ O 1
D23
I/ O 2
I/O 3
DM
DQ52
DQ53
DQ54
DQ55
DQS14
DQS14
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15
DQS DQS CS
I/O 0
I/O 1
D14
I/O 2
I/O 3
DM
DQS DQS CS
I/O 0
I/O 1
D32
I/O 2
I/O 3
DM
S1
S0
DQS4
DQS4
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS CS
D6
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS CS
D24
DM
DQS DQS CS
I/O 0
I/O 1
I/O 2
I/O 3
D15
DM
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D33
CS
DM
DQS DQS CS
I/ O 0
I/ O 1
I/ O 2
I/O 3
D7
DM
DQS DQS CS
I/ O 0
I/ O 1
D25
I/ O 2
I/O 3
DM
DQ52
DQ53
DQ54
DQ55
DQS DQS CS
I/O 0
I/O 1
I/O 2
I/O 3
D16
DM
DQS DQS
I/O
I/O
I/O
I/O
0
1
2
3
D34
CS
DM
1:2
BA0-BA2
A0-A15
R
E
G
I
S
T
E
R
RBA 0-RBA2
RA0-RA15
CKE0
CKE1
ODT0
ODT1
PCK7
Notes :
RCKE0
RCKE1
RODT0
RODT1
: SDRAMs D 0-D17
: SDRAMs D18-D35
BA0-BA2: SDRAMs D0-D35
A0-A15: SDRAMs D0-D35
: SDRAMs D 0-D 35
: SDRAMs D 0-D35
SDRAMs D 0 - D 35
CKE: SDRAMs D 0-D17
CKE: SDRAMs D18 -D35
ODT0: SDRAMs D0 - D17
ODT1: SDRAMs D 18- D35
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
Signals for Address and Command Parity Function
VSS
VDD
PAR_IN
100K Ohms
C0
C1
PAR _IN
Register A
PPO
VDD
VDD
C0
C1
PAR_IN
Register B
PPO
1. DQ-to-I/O wiring may be changed within a byte .
2. Resistor values without noted are 22 Ohms +/- 5%
3. A14 and A15 have the pull down resistors (100K
ohms), which is not indicated here .
4. RESET, PCK 7, and
connect to both registers.
Other signals connect to one of two registers .
CK0
P
L
L
PCK0-PCK6, PCK 8,PCK9
-
PCK7
,
,
Register CK
Register
CK:SDRAMs D0- D35
:SDRAMs D0- D35
REV 1.1
9/2008
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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