NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Feature
CAS Latency Frequency
DDR2-667
Speed Sorts
(CL-tRCD-tRP)
Parameter
Max. Clock Frequency
min
125
15
15
60
45
5
3.75
3
-
-
-3C
5-5-5
max
333
-
-
-
70K
8
8
8
-
-
min
125
12.5
12.5
57.5
45
5
3.75
2.5
2.5
-
DDR2-800
-AD
6-6-6
max
400
-
-
-
70K
8
8
8
8
-
tCK
(Avg.)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
tRCD
tRP
tRC
tRAS
tCK
(Avg.)
@
CL3
tCK
(Avg.)
@
CL4
tCK
(Avg.)
@
CL5
tCK
(Avg.)
@
CL6
tCK
(Avg.)
@
CL7
1.8V ± 0.1V Power Supply Voltage
8 internal memory banks
Programmable CAS Latency:
5 (DDR2-3C)
6 (DDR2-AD)
Data-Strobes: Bidirectional, Differential
1KB page size for x4 and x8
2KB page size for x16
Strong and Weak Strength Data-Output Driver
Auto-Refresh and Self-Refresh
Power Saving Power-Down modes
7.8 µs max. Average Periodic Refresh Interval
RoHS Compliance
Packages:
60-Ball BGA for x4 / x8 components
84-Ball BGA for x16 components
Programmable Additive Latency: 0, 1, 2, 3, 4 5
Write Latency = Read Latency -1
Programmable Burst Length:
4 and 8 Programmable Sequential / Interleave Burst
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
4 bit prefetch architecture
1
REV 1.0
06 / 2010
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Description
The 1giga-bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM
containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8 bank, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These
synchronous devices achieve high speed double-data-rate transfer rates of up to 800 Mb/sec/pin for general appli-
cations.
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance
adjustment and (5) an
ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4/x8 organized components
and A 13 bit address bus for x16 component is used to convey row, column, and bank address devices.
These devices operate with a single 1.8V ± 0.1V power supply and are available in BGA packages.
2
REV 1.0
06 / 2010
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration
–
60 balls BGA Package (x4)
< TOP View>
See the balls through the package
x4
1
VDD
NC
VDDQ
NC
VDDL
2
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA2
BA0
A10/ AP
VSS
A3
A7
VDD
A12
3
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VS
S
VDD
9
VDDQ
NC
VDDQ
NC
VDD
ODT
3
REV 1.0
06 / 2010
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration
–
60 balls BGA Package (x8)
< TOP View>
See the balls through the package
x8
1
VDD
DQ6
VDDQ
DQ4
VDDL
2
NU,/RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
BA2
BA0
A10/AP
VSS
A3
A7
VDD
A12
3
VSS
DM/RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
4
REV 1.0
06 / 2010
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration
–
84 balls BGA Package (x16)
< TOP View>
See the balls through the package
x 16
1
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
2
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA2
BA0
A10/ AP
VSS
A3
A7
VDD
A12
3
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA 1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
C
K
CK
CS
A0
A4
A8
NC
VSS
VDD
9
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
5
REV 1.0
06 / 2010
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