CMT60N03
N-C
HANNEL
Logic Level Power M
OSFET
APPLICATION
Buck Converter High Side Switch
Other Applications
V
DSS
30V
R
DS(ON)
Typ.
10.8mΩ
I
D
50A
FEATURES
Low ON Resistance
Low Gate Charge
Peak Current vs Pulse Width Curve
Inductive Switching Curves
Improved UIS Ruggedness
PIN CONFIGURATION
TO-252
TO-263
SYMBOL
D
Front View
Front View
D
SOURCE
DRAIN
GATE
G
1
2
3
S
G
1
2
3
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
Rating
Drain to Source Voltage (Note 1)
Drain to Current
－
Continuous Tc = 25℃, V
GS
@10V (Note 2)
－
Continuous Tc = 100℃, V
GS
@10V (Note 2)
－
Pulsed Tc = 25℃, V
GS
@10V (Note 3)
Gate-to-Source Voltage
－
Continue
Total Power Dissipation
Derating Factor above 25℃
Peak Diode Recovery dv/dt (Note 4)
Operating Junction and Storage Temperature Range
Single Pulse Avalanche Energy L=1.1mH,I
D
=30 Amps
Maximum Lead Temperature for Soldering Purposes
Maximum Package Body for 10 seconds
Pulsed Avalanche Rating
dv/dt
T
J
, T
STG
E
AS
T
L
T
PKG
I
AS
Symbol
V
DSS
I
D
I
D
I
DM
V
GS
P
D
Value
30
50
Fig.3
Fig.6
±20
52
0.5
3.0
-55 to 150
500
300
260
Fig.8
V
W
W/℃
V/ns
℃
mJ
℃
℃
Unit
V
A
THERMAL RESISTANCE
Symbol
R
θJC
R
θJA
R
θJA
Parameter
Junction-to-case
Junction-to-ambient
(PCB Mount)
Junction-to-ambient
Min
Typ
Max
2.4
50
62
Units
℃/W
℃/W
℃/W
Test Conditions
Water cooled heatsink, P
D
adjusted for a peak junction
temperature of +150℃
Minimum pad area, 2-oz copper, FR-4 circuit board, double
sided
1 cubic foot chamber, free air
2004/05/24
Preliminary
Champion Microelectronic Corporation
Page 1
CMT60N03
N-C
HANNEL
Logic Level Power M
OSFET
ORDERING INFORMATION
Part Number
CMT60N03N252
CMT60N03N263
Package
TO-252
TO-263
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, T
J
= 25℃.
CMT60N03
Characteristic
OFF Characteristics
Drain-to-Source Breakdown Voltage
(V
GS
= 0 V, I
D
= 250
μA)
Breakdown Voltage Temperature Coefficient, Fig.11
(Reference to 25
℃,
I
D
= 250
μA)
Drain-to-Source Leakage Current
(V
DS
= 24 V, V
GS
= 0 V, T
J
= 25℃)
(V
DS
= 24 V, V
GS
= 0 V, T
J
= 125℃)
Gate-to-Source Forward Leakage
(V
GS
= 20 V)
Gate-to-Source Reverse Leakage
(V
GS
= -20 V)
ON Characteristics
Gate Threshold Voltage,Fig.12
(V
DS
= V
GS
, I
D
= 250
μA)
Static Drain-to-Source On-Resistance, Fig.9,10
(V
GS
= 10 V, I
D
= 15A)
(V
GS
= 4.5 V, I
D
= 12A)
Forward Transconductance (V
DS
= 15 V, I
D
= 12A)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge (V
GS
= 10 V)
Total Gate Charge (V
GS
= 4.5 V)
Gate-to-Source Charge
Gate-to-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Continuous Source Current (Body
Diode Fig.16)
Pulse Source Current (Body Diode)
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Charge
(I
S
= 12 A, V
GS
= 0 V)
(I
F
= 12 A, V
GS
= 0 V,
d
i
/d
t
= 100A/µs)
Integral pn-diode in MOSFET
I
SM
V
SD
t
rr
Q
rr
25
31
Fig.6
1.0
38
46
A
V
ns
nC
(V
DS
= 15 V, I
D
= 12 A) (Note 6)
Fig.15
(Note 5)
Dynamic Characteristics
(V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz)
Fig.14
C
iss
C
oss
C
rss
Q
g
Q
g
Q
gs
Q
gd
Resistive Switching Characteristics
(V
DD
= 15 V, I
D
= 12 A,
V
GS
= 10 V,
R
G
= 1.0Ω) (Note 6)
(V
DD
= 15 V, I
D
= 12 A,
V
GS
= 4.5V,
R
G
= 1.0Ω) (Note 6)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
I
S
10
3.4
36
6.0
16
7.2
34
14
50
ns
ns
ns
ns
ns
ns
ns
ns
A
1520
314
152
27.9
14
4.9
4.3
35
19
pF
pF
pF
nC
nC
nC
nC
g
FS
(Note 5)
R
DS(on)
10.8
15.4
28
S
12.5
mΩ
V
GS(th)
1.0
3.0
V
I
GSS
-100
nA
I
GSS
I
DSS
1
10
100
nA
µA
ΔV
DSS
/∆T
J
27
mV/
℃
V
DSS
30
V
Symbol
Min
Typ
Max
Units
Source-Drain Diode Characteristics
2004/05/24
Preliminary
Champion Microelectronic Corporation
Page 2
CMT60N03
N-C
HANNEL
Logic Level Power M
OSFET
Note 1: T
J
= +25℃ to 150℃
Note 2: Current is calculated based upon maximum allowable junction temperature.
Package current limitation is 30A.
Note 3: Repetitive rating; pulse width limited by maximum junction temperature.
Note 4: I
SD
= 12.0A, di/dt
≤100A/µs,
V
DD
≤
BV
DSS
, T
J
= +150℃
Note 5: Pulse width
≤
250µs; duty cycle
≤
2%
Note 6: Essentially independent of operating temerpature.
2004/05/24
Preliminary
Champion Microelectronic Corporation
Page 3
CMT60N03
N-C
HANNEL
Logic Level Power M
OSFET
Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
1.00
Duty Cycle
50%
20%
10%
P
DM
Z
θJC
,
Thermal Impedance
0.10
5%
2%
1%
single pulse
t
1
t
2
NOTES:
DUTY FACTOR: D=t1/t2
PEAK T
J
=P
DM
x Z
θJC
x R
θJC
+T
C
0.01
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
t
p
, Rectangular Pulse Duration (Seconds)
Figure 2. Maximum Power Dissipation
vs Case Temperature
60
35
Figure 3. Maximum Continuous Drain Current
vs Case Temperature
P
D
, Power Dissipation (W)
I
D
, Drain Current (A)
50
40
30
20
10
0
25
50
75
100
125
150
30
25
20
15
10
5
0
25
50
75
100
125
150
T
C
, Case Temperature (
o
C)
T
C
, Case Temperature (
o
C)
Figure 4. Typical Output Characteristics
100
90
V
GS
= 10V
Figure 5. Typical Drain-to-Source ON Resistance
vs Gate Voltage and Drain Current
0.10
0.09
I
D
= 7A
I
D
= 14 A
I
D
= 28 A
I
D
= 55 A
R
DS(ON),
Drain-to-Source
I
D
, Drain Current (A)
80
70
60
50
40
30
20
10
0
0
5
PULSE DURATION = 250 µS
DUTY CYCLE = 0.5% MAX
o
T
C
= 25 C
V
GS
= 4.5V
0.08
ON Resistance (Ω)
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
PULSE DURATION = 250 µS
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 4.0V
V
GS
= 3.7V
V
GS
= 3.5V
V
GS
= 3.3V
V
GS
= 3.0V
V
GS
= 2.7V
V
GS
= 2.5V
10
15
20
2
3
4
5
6
7
8
9
10
V
DS
, Drain-to-Source Voltage (V)
V
GS
, Gate-to-Source Voltage (V)
2004/05/24
Preliminary
Champion Microelectronic Corporation
Page
4
CMT60N03
N-C
HANNEL
Logic Level Power M
OSFET
Figure 6. Maximum Peak Current Capability
10000
TRANSCONDUCTANCE
MAY LIMIT CURRENT IN
THIS REGION
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
I
=
I
25
150 –
T C
----------------------
125
I
DM
, Peak Current (A)
1000
100
10
V
GS
=
10V
1
1E-6
10E-6
100E-6
1E-3
10E-3
100E-3
1E+0
10E+0
t
p,
Pulse Width (Seconds)
Figure 7. Typical Transfer Characteristics
30
Figure 8. Unclamped Inductive Switching Capability
1000
I
D
, Drain-to-Source Current (A)
25
20
15
10
5
0
1.0
I
AS
, Avalanche Current (A)
PULSE DURATION = 250 µS
DUTY CYCLE = 0.5% MAX
VDS = 15 V
If R≠ 0: t
AV
= (L/R) ln[I
AS
×R)/(1.3BV
DSS
-V
DD
)+1]
If R= 0: t
AV
= (L×I
AS
)/(1.3BV
DSS
-V
DD
)
R equals total Series resistance of Drain circuit
100
STARTING T
J
= 25
o
C
+150
o
C
+25
o
C
-55
o
C
10
STARTING T
J
= 150
o
C
1.5
2.0
2.5
3.0
3.5
4.0
1
1E-6
10E-6
100E-6
1E-3
10E-3
100E-3
V
GS
, Gate-to-Source Voltage (V)
t
AV
, Time in Avalanche (Seconds)
Figure 9. Typical Drain-to-Source ON Resistance
vs Drain Current
R
DS(ON)
,
Drain-to-Source ON Resistance (mΩ)
100
RDS(ON), Drain-to-Source
Resistance (Normalized)
PULSE DURATION = 10 µS
DUTY CYCLE = 0.5% MAX
TC=25°C
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
Figure 10. Typical Drain-to-Source ON Resistance
vs Junction Temperature
V
GS
= 4.5V
V
GS
= 10 V
PULSE DURATION = 250 µS
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 15A
10
0
50
100
150
200
250
300
350
400
-75
-50
-25
0
25
50
75
100 125
150
I
D
, Drain Current (A)
T
J
, Junction Temperature (
o
C)
2004/05/24
Preliminary
Champion Microelectronic Corporation
Page
5
FPGA/CPLD
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