NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM
32Mx64 bit Two Bank Small Outline SDRAM Module
based on 16Mx16, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
Features
l
144 Pin JEDEC Standard, 8 Byte Small Outline Dual-In-line
Memory Module
l
l
l
l
l
l
l
l
l
l
32Mx64 Synchronous DRAM SO DIMM
Inputs and outputs are LVTTL (3.3V) compatible
10 Ohm Resistors on DQs
Single 3.3V
±
0.3V Power Supply
Single Pulsed
RAS
interface
SDRAMs have four internal banks
Fully Synchronous to positive Clock Edge
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
l
l
l
l
l
l
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8,
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
Suspend Mode and Power Down Mode
13/9/2 Addressing (Row/Column/Bank)
8192 refresh cycles distributed across 64ms
Serial Presence Detect
Gold contacts
Description
NT256S64VH8A0GM is a 144-pin Synchronous DRAM Small Outline Dual In-line Memory Module (SO DIMM) that is organized as a 32Mx64
high-speed memory array. The SO DIMM uses eight 16Mx16 SDRAMs in 400mil TSOP II packages and achieves high-speed data transfer
rates of up to 133 MHz by employing a prefetch / pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst
power.
All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are
sampled at the positive edge of the externally supplied clock (CK0,CK1). Internal operating modes are defined by combinations of the
RAS
,
CAS
,
WE
,
S0
,
S1
, DQMB, and CKE0, CKE1signals. A command decoder initiates the necessary timings for each operation.
Prior to any access operation, the
CAS
latency, burst type, burst length, and burst operation type must be programmed into the SO DIMM by
address inputs A0-A9 during the mode register set cycle. The SO DIMM uses serial presence detects implemented via a serial EEPROM using
the two pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.
All Nanya 144-pin SO DIMMs provide a high performance, flexible 8-byte interface in a 2.66" long space-saving footprint.
Ordering Information
Speed
Part Number
MHz.
143MHz
NT256S64VH8A0GM-7K
133MHz
133MHz
NT256S64VH8A0GM-75B
100MHz
125MHz
NT256S64VH8A0GM-8B
100MHz
* CL = CAS Latency
2
2
2
2
3
2
3
2
3
2
3
2
3
2
3
32Mx64
Gold
3.3V
CL
3
t RCD
3
t RP
3
Organization
Leads
Power
PRELIMINARY
08 / 2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM
Pin Description
CK0,CK1
CKE0,CKE1
Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address
DQ0-DQ63
DQMB0-DQMB7
V
DD
V
SS
NC
SCL
SDA
DU
Data input/output
Data Mask
Power (3.3V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Don’ use
t
RAS
CAS
WE
S0
,
S1
A0-A9, A11,A12
A10 / AP
BA0, BA1
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQMB0
DQMB1
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQMB4
DQMB5
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
CK0
V
DD
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
CKE0
V
DD
Voltage Key
Pin
51
53
55
57
59
Front
DQ14
DQ15
V
SS
NC
NC
Pin
52
54
56
58
60
Back
DQ46
DQ47
V
SS
NC
NC
Pin
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10/ AP
V
DD
DQMB2
DQMB3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
DD
Pin
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
BA1
A11
V
DD
DQMB6
DQMB7
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
V
DD
RAS
CAS
CKE1
A12
NC
CK1
V
SS
NC
NC
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
WE
S0
S1
DU
V
SS
NC
NC
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
Note: All pin assignments are consistent for all 8-byte versions.
PRELIMINARY
08 / 2001
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM
SDRAM DIMM Block Diagram
(2 Bank, 16Mx16 SDRAMs)
S1
S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
D0
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D4
DQ39
D2
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D6
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D1
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D5
DQ55
D3
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D7
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RAS
CAS
CKE0
CKE1
WE
A0-A12
BA0
BA1
DQn
SDRAMs D0-D7
SDRAMs D0-D7
SDRAMs D0-D3
SDRAMs D4-D7
SDRAMs D0-D7
SPD
SCL
A0
A1
A2
SDA
CK0 / CK1
D0 / D4
D1 / D5
D2 / D6
D3 / D7
10ohm
V
DD
SDRAMs D0-D7
SDRAMs D0-D7
SDRAMs D0-D7
Every DQ pin of SDRAM
V
SS
D0 - D7
D0 - D7
CK1
10pF
PRELIMINARY
08 / 2001
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM
Input/Output Functional Description
Symbol
CK0, CK1
Type
Input
Signal
Pulse
Edge
Active
CKE0, CKE1
Input
Level
High
the Self-Refresh mode.
Enables the associated SDRAM command decoder when low and disables the
Active
By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or
their associated clock.
Activates the SDRAM CK0 and CK1 signals when high and deactivates them when low.
Polarity
Positive
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
S0
,
S1
Input
Pulse
Low
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
RAS
,
CAS
,
WE
BA0, BA1
Active
Input
Input
Pulse
Low
Level
-
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
operation to be executed by the SDRAM.
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
A0 - A9
A10/AP
A11, A12
Input
Level
-
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Input
Data and Check Bit input/output pins operate in the same manner as on conventional
Level
/Output
-
DRAMs.
The Data input/output mask places the DQ buffers in a high impedance state when
sampled high. In Read mode, DQM has a latency of two clock cycles and controls the
Active
DQ0 - DQ63
DQMB0 -DQMB7
Input
Pulse
High
output buffers like an output enable. In Write mode, DQM has a latency of zero and
operates as a byte mask by allowing input data to be written if it is low but blocks the
Write operation if DQM is high.
Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence
Input
SDA
/Output
pull-up resistor is required on the system board.
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
SCL
Input
Pulse
-
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
V
DD
, V
SS
Supply
Power and ground for the module.
Level
-
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
PRELIMINARY
08 / 2001
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM
Absolute Maximum Ratings
Symbol
V
DD,
V
DDQ
V
IN,
V
OUT
T
A
T
STG
P
D
I
OUT
Parameter
Voltage on V
DD
relative to V
SS
Voltage on Any Pin to V
SS
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
Short Circuit Output Current
Rating
-0.3 to +4.6
V
-0.3 to V
DD
+ 0.3
0 to +70
-55 to +125
8
50
1
1
1
1
1
Units
Notes
°C
°C
W
mA
1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
(T
A
=0 to 70
°C)
Rating
Symbol
V
DD
V
IH
V
IL
V
OH
V
OL
I
IL
1.
2.
3.
Power Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage current
Parameter
Min.
3.0
2.0
-0.3
2.4
-
-10
Typ.
3.3
-
-
-
-
-
Max.
3.6
V
DD
+ 0.3
0.8
-
0.4
10
V
V
V
V
V
µA
1
1,2
1,3
Units
Notes
All voltages referenced to V
SS
.
V
IH
(max) = V
DD
/ V
DDQ
+ 1.2V for pulse width
≤
5ns
V
IL
(min) = V
SS
/ V
SSQ
- 1.2V for pulse width
≤
5ns .
Capacitance
(T
A
=25
°C
, f =1MHz, V
DD
=3.3 ± 0.3V)
Symbol
C
I1
C
I2
C
I3
C
I4
C
I5
C
I6
C
IO1
C
IO2
Parameter
Input Capacitance (A0-A9, A10/AP, A11, A12, BA0, BA1,
RAS
,
CAS
,
WE
)
Input Capacitance (CKE0,CKE1)
Input Capacitance (
S0
,
S1
)
Input Capacitance (CK0,CK1 )
Input Capacitance (DQMB0 - DQMB7)
Input Capacitance (SCL)
Input/Output Capacitance (DQ0 - DQ63)
Input/Output Capacitance (SDA)
Max.
52
46
35
30
15
13
18
15
pF
Unit
DC Output Load Circuit
3.3 V
1200 ohms
Output
50 pF
870 ohms
VOH(DC) = 2.4V,IOH= -2mA
VOL(DC) = 0.4V,IOL= -2mA
PRELIMINARY
08 / 2001
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
