ESMT
SDRAM
M12L16161A (2Q)
Automotive Grade
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency (2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
(self refresh is not supported for VA grade)
Refresh
-
32ms refresh period (2K cycle) for V grade
-
16ms refresh period (2K cycle) for VA grade
GENERAL DESCRIPTION
The M12L16161A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID
Max Freq.
Package
Comments
Automotive range (V): -40℃ to +85℃
M12L16161A-5TVG2Q
M12L16161A-7TVG2Q
200MHz
143MHz
50 pin TSOP(II)
50 pin TSOP(II)
Pb-free
Pb-free
Automotive range (VA): -40℃ to +105℃
M12L16161A-5TVAG2Q
M12L16161A-7TVAG2Q
200MHz
143MHz
50 pin TSOP(II)
50 pin TSOP(II)
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jan. 2012
Revision
:
1.0
1/29
ESMT
FUNCTIONAL BLOCK DIAGRAM
M12L16161A (2Q)
Automotive Grade
I/O Control
Bank Select
Data Input Register
LWE
LDQM
Row Buffer
Refresh Counter
Row Decoder
Sense AMP
Output Buffer
512K x 16
512K x 16
Address Register
LRAS
CLK
DQi
CLK
ADD
LCBR
LRAS
Col. Buffer
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CKE
L(U)DQM
CS
RAS
CAS
WE
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jan. 2012
Revision
:
1.0
2/29
ESMT
PIN CONFIGURATION (TOP VIEW)
M12L16161A (2Q)
Automotive Grade
(TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10/AP
BA
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
L(U)DQM
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jan. 2012
Revision
:
1.0
3/29
ESMT
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
T
A
(V grade)
T
A
(VA grade)
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-40 ~ +85
-40 ~ +105
-55 ~ + 150
0.7
50
M12L16161A (2Q)
Automotive Grade
Unit
V
V
°
C
°
C
°
C
W
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
,V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
uA
uA
1
2
I
OH
=-2mA
I
OL
= 2mA
3
4
Note
1.V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2.V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3.Any input 0V
≤
V
IN
≤
V
DD
, all other pins are not under test = 0V.
4.Dout is disabled, 0V
≤
V
OUT
≤
V
DD
.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°C
, f = 1MHz)
Pin
CLOCK
RAS , CAS ,
WE
, CS , CKE, LDQM,
UDQM
ADDRESS
DQ0 ~DQ15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jan. 2012
Revision
:
1.0
4/29
ESMT
DC CHARACTERISTICS
M12L16161A (2Q)
Automotive Grade
(Recommended operating condition unless otherwise noted, V
IH
(min)/V
IL
(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Test Condition
CAS
Latency
Version
-5
100
2
2
25
mA
-7
80
Unit Note
I
CC1
I
CC2P
I
CC2PS
I
CC2N
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA, Page Burst
All Band Activated, t
CCD
= t
CCD
(min)
t
RFC
≥
t
RFC
(min)
CKE
≤
0.2V
3
2
mA
1
mA
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3P
I
CC3PS
10
10
10
mA
mA
I
CC3N
25
mA
I
CC3NS
I
CC4
10
100
100
100
1
80
80
80
mA
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
mA
mA
mA
1
2
I
CC5
I
CC6
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is t
REF
(max). Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jan. 2012
Revision
:
1.0
5/29
单片机
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