Chrontel
CH7317B
CH7317B SDVO
◊
/ RGB DAC
Features
•
•
•
•
•
•
•
•
Supporting analog RGB outputs for a display
monitor
Supporting maximum pixel rate of 165MP/s or
graphics resolutions up to 1920x1200*
High-speed SDVO
◊
(1G~2Gbps) AC-coupled serial
differential RGB inputs
Supporting monitor connection detection
Programmable power management
Fully programmable through serial port
Configuration through Intel
®
SDVO Opcode
◊
Offered in 64-pin LQFP package and 64-pin QFN
package
General Description
The CH7317B is a Display Controller device interfaces
seamlessly to HDTV or PC monitors that is equipped with a
VGA RGB interface display connector. Its input port,
complied with Intel SDVO Specification 1.2, can accept a
digital graphics, high-speed, AC-coupled, serial-
differential RGB input signal, and convert it to analog RGB
signal for driving the display.
The CH7317B supports maximum pixel rate of 165MP/s and
is capable of displaying up to 1920x1200 resolution with
reduced blanking. The built-in serial port controller will allow
the graphics chipset to obtain the monitor’s EDID information
or communicate with CH7317B internal registers through
SDVO Opcodes. In addition, the transmitter is designed with
a monitor connection detection algorithm that allows the
graphics chipset to read back the connection status through
CH7317B internal registers.
The CH7317B provides the Boundary-scan test to help
system developers to check the interconnection between
chip I/O and the printed circuit board for faults. When
the device is powered down by the graphics chipset, its
current consumption is less than 100uA. The CH7317B is
available in 64-pin LQFP and 64-pin QFN packages.
* Reduced Blanking
◊
Intel
®
Proprietary.
Serial
Port
Control
AS
SPC
SPD
RESET*
SC _D DC
SD _D DC
SC _PRO M
SD _PRO M
SD VO_ Clk(+,-)
2
C lock
D river
2
VSYN C,
HSYN C
D AC 2
SDVO_R(+,-)
SDVO_G(+,-)
SDVO_B(+,-)
DAC2
DAC1
DAC0
ISET
6
Data Latch,
Serial to Parallel
10 bit-8 bit
decoder
D AC 1
D AC 0
10 bit DAC
Figure 1: Functional Block Diagram
201-0000-097
Rev. 1.8,
1/07/2014
1
CHRONTEL
Table of Contents
1.0
1.1
1.2
CH7317B
Pin-Out ____________________________________________________________________ 4
Package Diagram ___________________________________________________________________4
Pin Description _____________________________________________________________________6
2.0
2.1
2.2
2.3
Functional Description________________________________________________________ 8
Input Interface______________________________________________________________________8
VGA Output Operation_______________________________________________________________8
Command Interface _________________________________________________________________9
3.0
4.0
4.1
4.2
4.3
4.4
4.5
Register Control ____________________________________________________________ 12
Electrical Specifications ______________________________________________________ 13
Absolute Maximum Ratings __________________________________________________________13
Recommended Operating Conditions ___________________________________________________13
Electrical Characteristics ____________________________________________________________14
DC Specifications __________________________________________________________________14
AC Specifications __________________________________________________________________16
5.0
6.0
Package Dimensions _________________________________________________________ 18
Revision History ____________________________________________________________ 20
2
201-0000-097
Rev. 1.8,
1/07/2014
CHRONTEL
Figures and Tables
List of Figures
CH7317B
Figure 1: Functional Block Diagram ....................................................................................................................................1
Figure 2: 64-Pin LQFP Package ...........................................................................................................................................4
Figure 3: 64-Pin QFN Package.............................................................................................................................................5
Figure 4: Control Bus Switch .............................................................................................................................................10
Figure 5: NAND Tree Connection .....................................................................................................................................10
Figure 6: 64 Pin LQFP Package .........................................................................................................................................18
Figure 7: 64 Pin QFN Package (8 X 8 mm)........................................................................................................................19
List of Tables
Table 1: Pin Description .......................................................................................................................................................6
Table 2: CH7317B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns ..........................................8
Table 3: Various VGA resolutions. ......................................................................................................................................9
Table 4: Video DAC Configurations for CH7317B .............................................................................................................9
Table 5: Signal Order in the NAND Tree Testing ..............................................................................................................11
Table 6: Signals not Tested in NAND Test besides power pins .........................................................................................11
Table 7: Revisions ..............................................................................................................................................................20
201-0000-097
Rev. 1.8,
1/07/2014
3
CHRONTEL
1.0 Pin-Out
1.1
Package Diagram
CH7317B
SDVO_CLK+
AGND
SDVO_B-
SDVO_CLK-
SDVO_G-
SDVO_G+
SDVO_R-
SDVO_R+
SDVO_B+
AGND
AVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
RPLL
T1
SD_DDC
SC_DDC
SD_PROM
SC_PROM
NC
RESET*
AS
NC
DGND
SPD
SPC
DVDD
BSCAN
Reserved
VDAC2
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
AVDD
AVDD
T2
Reserved
Reserved
Reserved
NC
NC
NC
NC
NC
NC
NC
NC
DGND
VSYNC
DVDD
HSYNC
NC
Chrontel
CH7317B
DACA[2]
DACA[1]
DACA[0]
NC
GDAC2
GDAC1
VDAC1
VDAC0
GDAC0
NC
NC
NC
NC
NC
Figure 2: 64-Pin LQFP Package
4
201-0000-097
ISET
NC
Rev. 1.8,
1/07/2014
CHRONTEL
CH7317B
SDVO_CLK-
SDVO_CLK+
SDVO_G+
SDVO_R+
SDVO_B+
AVDD
SDVO_G-
AGND
SDVO_R-
AGND
SDVO_B-
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
AVDD
AVDD
T2
RPLL
T1
SD_DDC
SC_DDC
SD_PROM
SC_PROM
NC
RESET*
AS
NC
DGND
SPD
SPC
DVDD
BSCAN
Reserved
VDAC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
Reserved
Reserved
Reserved
NC
NC
NC
NC
NC
NC
NC
NC
DGND
VSYNC
DVDD
HSYNC
NC
Chrontel
CH7317
7317B
CH7317B
VDAC1
DACA[2]
DACA[0]
NC
DACA[1]
GDAC2
GDAC1
Figure 3: 64-Pin QFN Package
201-0000-097
Rev. 1.8,
1/07/2014
GDAC0
VDAC0
ISET
NC
NC
NC
NC
NC
NC
5
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